comparison CircuitNetlistCreator.c @ 18:b0e9969d8d15

first runnable version (very buggy)
author hausers
date Mon, 20 Feb 2012 19:07:31 +0100
parents fa277c6ce6f2
children ba3883d39e62
comparison
equal deleted inserted replaced
5:b08f772a9507 6:cef1de1e9e77
17 commPath->idxOfToElem = toElIdx; \ 17 commPath->idxOfToElem = toElIdx; \
18 commPath->idxOfToInPort = inPort; \ 18 commPath->idxOfToInPort = inPort; \
19 commPath->commTimeCalcFn = timeFnPtr;\ 19 commPath->commTimeCalcFn = timeFnPtr;\
20 commPath->archSpecCommPathData = dataPtr; \ 20 commPath->archSpecCommPathData = dataPtr; \
21 }while(0); //macro magic for namespace 21 }while(0); //macro magic for namespace
22
22 23
23 24
24 HWSimActivityType* createPingPongActivityType (); 25 HWSimActivityType* createPingPongActivityType ();
25 26
26 HWSimElem* createAPingPongElem (HWSimNetlist *netlist); 27 HWSimElem* createAPingPongElem (HWSimNetlist *netlist);
76 numCommPaths = 2; 77 numCommPaths = 2;
77 commPaths = malloc( numCommPaths * sizeof(HWSimCommPath) ); 78 commPaths = malloc( numCommPaths * sizeof(HWSimCommPath) );
78 netlist->numCommPaths= numCommPaths; 79 netlist->numCommPaths= numCommPaths;
79 netlist->commPaths= commPaths; 80 netlist->commPaths= commPaths;
80 //TL 0, out-port 0 to TL 1, in-port 0 81 //TL 0, out-port 0 to TL 1, in-port 0
82 commPaths[0]= malloc(sizeof(HWSimCommPath));
81 setCommPathValuesTo(commPaths[0],0,0,1,0, commPath_TimeSpanCalc, NULL); 83 setCommPathValuesTo(commPaths[0],0,0,1,0, commPath_TimeSpanCalc, NULL);
82 //TL 1, out-port 0 to TL 0, in-port 0 84 //TL 1, out-port 0 to TL 0, in-port 0
85 commPaths[1]= malloc(sizeof(HWSimCommPath));
83 setCommPathValuesTo(commPaths[1], 1,0,0,0, commPath_TimeSpanCalc, NULL); 86 setCommPathValuesTo(commPaths[1], 1,0,0,0, commPath_TimeSpanCalc, NULL);
84 87
85 //TODO: decide how do in-out bidirectional commPaths -- thinking make it two 88 //TODO: decide how do in-out bidirectional commPaths -- thinking make it two
86 // separate commPaths with guard between in-port and out-port 89 // separate commPaths with guard between in-port and out-port
87 90