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diff libavcodec/arm/mdct_neon.S @ 2:897f711a7157
rearrange to work with autoconf
| author | Nina Engelhardt <nengel@mailbox.tu-berlin.de> |
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| date | Tue, 25 Sep 2012 15:55:33 +0200 |
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1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/libavcodec/arm/mdct_neon.S Tue Sep 25 15:55:33 2012 +0200 1.3 @@ -0,0 +1,303 @@ 1.4 +/* 1.5 + * ARM NEON optimised MDCT 1.6 + * Copyright (c) 2009 Mans Rullgard <mans@mansr.com> 1.7 + * 1.8 + * This file is part of FFmpeg. 1.9 + * 1.10 + * FFmpeg is free software; you can redistribute it and/or 1.11 + * modify it under the terms of the GNU Lesser General Public 1.12 + * License as published by the Free Software Foundation; either 1.13 + * version 2.1 of the License, or (at your option) any later version. 1.14 + * 1.15 + * FFmpeg is distributed in the hope that it will be useful, 1.16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of 1.17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1.18 + * Lesser General Public License for more details. 1.19 + * 1.20 + * You should have received a copy of the GNU Lesser General Public 1.21 + * License along with FFmpeg; if not, write to the Free Software 1.22 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA 1.23 + */ 1.24 + 1.25 +#include "asm.S" 1.26 + 1.27 + preserve8 1.28 + 1.29 + .text 1.30 + 1.31 +#define ff_fft_calc_neon X(ff_fft_calc_neon) 1.32 + 1.33 +function ff_imdct_half_neon, export=1 1.34 + push {r4-r8,lr} 1.35 + 1.36 + mov r12, #1 1.37 + ldr lr, [r0, #28] @ mdct_bits 1.38 + ldr r4, [r0, #32] @ tcos 1.39 + ldr r3, [r0, #8] @ revtab 1.40 + lsl r12, r12, lr @ n = 1 << nbits 1.41 + lsr lr, r12, #2 @ n4 = n >> 2 1.42 + add r7, r2, r12, lsl #1 1.43 + mov r12, #-16 1.44 + sub r7, r7, #16 1.45 + 1.46 + vld2.32 {d16-d17},[r7,:128],r12 @ d16=x,n1 d17=x,n0 1.47 + vld2.32 {d0-d1}, [r2,:128]! @ d0 =m0,x d1 =m1,x 1.48 + vrev64.32 d17, d17 1.49 + vld2.32 {d2,d3}, [r4,:128]! @ d2=c0,c1 d3=s0,s2 1.50 + vmul.f32 d6, d17, d2 1.51 + vmul.f32 d7, d0, d2 1.52 +1: 1.53 + subs lr, lr, #2 1.54 + ldr r6, [r3], #4 1.55 + vmul.f32 d4, d0, d3 1.56 + vmul.f32 d5, d17, d3 1.57 + vsub.f32 d4, d6, d4 1.58 + vadd.f32 d5, d5, d7 1.59 + uxth r8, r6, ror #16 1.60 + uxth r6, r6 1.61 + add r8, r1, r8, lsl #3 1.62 + add r6, r1, r6, lsl #3 1.63 + beq 1f 1.64 + vld2.32 {d16-d17},[r7,:128],r12 1.65 + vld2.32 {d0-d1}, [r2,:128]! 1.66 + vrev64.32 d17, d17 1.67 + vld2.32 {d2,d3}, [r4,:128]! @ d2=c0,c1 d3=s0,s2 1.68 + vmul.f32 d6, d17, d2 1.69 + vmul.f32 d7, d0, d2 1.70 + vst2.32 {d4[0],d5[0]}, [r6,:64] 1.71 + vst2.32 {d4[1],d5[1]}, [r8,:64] 1.72 + b 1b 1.73 +1: 1.74 + vst2.32 {d4[0],d5[0]}, [r6,:64] 1.75 + vst2.32 {d4[1],d5[1]}, [r8,:64] 1.76 + 1.77 + mov r4, r0 1.78 + mov r6, r1 1.79 + bl ff_fft_calc_neon 1.80 + 1.81 + mov r12, #1 1.82 + ldr lr, [r4, #28] @ mdct_bits 1.83 + ldr r4, [r4, #32] @ tcos 1.84 + lsl r12, r12, lr @ n = 1 << nbits 1.85 + lsr lr, r12, #3 @ n8 = n >> 3 1.86 + 1.87 + add r4, r4, lr, lsl #3 1.88 + add r6, r6, lr, lsl #3 1.89 + sub r1, r4, #16 1.90 + sub r3, r6, #16 1.91 + 1.92 + mov r7, #-16 1.93 + mov r8, r6 1.94 + mov r0, r3 1.95 + 1.96 + vld2.32 {d0-d1}, [r3,:128], r7 @ d0 =i1,r1 d1 =i0,r0 1.97 + vld2.32 {d20-d21},[r6,:128]! @ d20=i2,r2 d21=i3,r3 1.98 + vld2.32 {d16,d18},[r1,:128], r7 @ d16=c1,c0 d18=s1,s0 1.99 +1: 1.100 + subs lr, lr, #2 1.101 + vmul.f32 d7, d0, d18 1.102 + vld2.32 {d17,d19},[r4,:128]! @ d17=c2,c3 d19=s2,s3 1.103 + vmul.f32 d4, d1, d18 1.104 + vmul.f32 d5, d21, d19 1.105 + vmul.f32 d6, d20, d19 1.106 + vmul.f32 d22, d1, d16 1.107 + vmul.f32 d23, d21, d17 1.108 + vmul.f32 d24, d0, d16 1.109 + vmul.f32 d25, d20, d17 1.110 + vadd.f32 d7, d7, d22 1.111 + vadd.f32 d6, d6, d23 1.112 + vsub.f32 d4, d4, d24 1.113 + vsub.f32 d5, d5, d25 1.114 + beq 1f 1.115 + vld2.32 {d0-d1}, [r3,:128], r7 1.116 + vld2.32 {d20-d21},[r6,:128]! 1.117 + vld2.32 {d16,d18},[r1,:128], r7 @ d16=c1,c0 d18=s1,s0 1.118 + vrev64.32 q3, q3 1.119 + vst2.32 {d4,d6}, [r0,:128], r7 1.120 + vst2.32 {d5,d7}, [r8,:128]! 1.121 + b 1b 1.122 +1: 1.123 + vrev64.32 q3, q3 1.124 + vst2.32 {d4,d6}, [r0,:128] 1.125 + vst2.32 {d5,d7}, [r8,:128] 1.126 + 1.127 + pop {r4-r8,pc} 1.128 +endfunc 1.129 + 1.130 +function ff_imdct_calc_neon, export=1 1.131 + push {r4-r6,lr} 1.132 + 1.133 + ldr r3, [r0, #28] 1.134 + mov r4, #1 1.135 + mov r5, r1 1.136 + lsl r4, r4, r3 1.137 + add r1, r1, r4 1.138 + 1.139 + bl ff_imdct_half_neon 1.140 + 1.141 + add r0, r5, r4, lsl #2 1.142 + add r1, r5, r4, lsl #1 1.143 + sub r0, r0, #8 1.144 + sub r2, r1, #16 1.145 + mov r3, #-16 1.146 + mov r6, #-8 1.147 + vmov.i32 d30, #1<<31 1.148 +1: 1.149 + vld1.32 {d0-d1}, [r2,:128], r3 1.150 + pld [r0, #-16] 1.151 + vrev64.32 q0, q0 1.152 + vld1.32 {d2-d3}, [r1,:128]! 1.153 + veor d4, d1, d30 1.154 + pld [r2, #-16] 1.155 + vrev64.32 q1, q1 1.156 + veor d5, d0, d30 1.157 + vst1.32 {d2}, [r0,:64], r6 1.158 + vst1.32 {d3}, [r0,:64], r6 1.159 + vst1.32 {d4-d5}, [r5,:128]! 1.160 + subs r4, r4, #16 1.161 + bgt 1b 1.162 + 1.163 + pop {r4-r6,pc} 1.164 +endfunc 1.165 + 1.166 +function ff_mdct_calc_neon, export=1 1.167 + push {r4-r10,lr} 1.168 + 1.169 + mov r12, #1 1.170 + ldr lr, [r0, #28] @ mdct_bits 1.171 + ldr r4, [r0, #32] @ tcos 1.172 + ldr r3, [r0, #8] @ revtab 1.173 + lsl lr, r12, lr @ n = 1 << nbits 1.174 + add r7, r2, lr @ in4u 1.175 + sub r9, r7, #16 @ in4d 1.176 + add r2, r7, lr, lsl #1 @ in3u 1.177 + add r8, r9, lr, lsl #1 @ in3d 1.178 + add r5, r4, lr, lsl #1 1.179 + sub r5, r5, #16 1.180 + sub r3, r3, #4 1.181 + mov r12, #-16 1.182 + 1.183 + vld2.32 {d16,d18},[r9,:128],r12 @ in0u0,in0u1 in4d1,in4d0 1.184 + vld2.32 {d17,d19},[r8,:128],r12 @ in2u0,in2u1 in3d1,in3d0 1.185 + vld2.32 {d0, d2}, [r7,:128]! @ in4u0,in4u1 in2d1,in2d0 1.186 + vrev64.32 q9, q9 @ in4d0,in4d1 in3d0,in3d1 1.187 + vld2.32 {d1, d3}, [r2,:128]! @ in3u0,in3u1 in1d1,in1d0 1.188 + vsub.f32 d0, d18, d0 @ in4d-in4u I 1.189 + vld2.32 {d20,d21},[r4,:128]! @ c0,c1 s0,s1 1.190 + vrev64.32 q1, q1 @ in2d0,in2d1 in1d0,in1d1 1.191 + vld2.32 {d30,d31},[r5,:128],r12 @ c2,c3 s2,s3 1.192 + vadd.f32 d1, d1, d19 @ in3u+in3d -R 1.193 + vsub.f32 d16, d16, d2 @ in0u-in2d R 1.194 + vadd.f32 d17, d17, d3 @ in2u+in1d -I 1.195 +1: 1.196 + vmul.f32 d7, d0, d21 @ I*s 1.197 + ldr r10, [r3, lr, lsr #1] 1.198 + vmul.f32 d6, d1, d20 @ -R*c 1.199 + ldr r6, [r3, #4]! 1.200 + vmul.f32 d4, d1, d21 @ -R*s 1.201 + vmul.f32 d5, d0, d20 @ I*c 1.202 + vmul.f32 d24, d16, d30 @ R*c 1.203 + vmul.f32 d25, d17, d31 @ -I*s 1.204 + vmul.f32 d22, d16, d31 @ R*s 1.205 + vmul.f32 d23, d17, d30 @ I*c 1.206 + subs lr, lr, #16 1.207 + vsub.f32 d6, d6, d7 @ -R*c-I*s 1.208 + vadd.f32 d7, d4, d5 @ -R*s+I*c 1.209 + vsub.f32 d24, d25, d24 @ I*s-R*c 1.210 + vadd.f32 d25, d22, d23 @ R*s-I*c 1.211 + beq 1f 1.212 + mov r12, #-16 1.213 + vld2.32 {d16,d18},[r9,:128],r12 @ in0u0,in0u1 in4d1,in4d0 1.214 + vld2.32 {d17,d19},[r8,:128],r12 @ in2u0,in2u1 in3d1,in3d0 1.215 + vneg.f32 d7, d7 @ R*s-I*c 1.216 + vld2.32 {d0, d2}, [r7,:128]! @ in4u0,in4u1 in2d1,in2d0 1.217 + vrev64.32 q9, q9 @ in4d0,in4d1 in3d0,in3d1 1.218 + vld2.32 {d1, d3}, [r2,:128]! @ in3u0,in3u1 in1d1,in1d0 1.219 + vsub.f32 d0, d18, d0 @ in4d-in4u I 1.220 + vld2.32 {d20,d21},[r4,:128]! @ c0,c1 s0,s1 1.221 + vrev64.32 q1, q1 @ in2d0,in2d1 in1d0,in1d1 1.222 + vld2.32 {d30,d31},[r5,:128],r12 @ c2,c3 s2,s3 1.223 + vadd.f32 d1, d1, d19 @ in3u+in3d -R 1.224 + vsub.f32 d16, d16, d2 @ in0u-in2d R 1.225 + vadd.f32 d17, d17, d3 @ in2u+in1d -I 1.226 + uxth r12, r6, ror #16 1.227 + uxth r6, r6 1.228 + add r12, r1, r12, lsl #3 1.229 + add r6, r1, r6, lsl #3 1.230 + vst2.32 {d6[0],d7[0]}, [r6,:64] 1.231 + vst2.32 {d6[1],d7[1]}, [r12,:64] 1.232 + uxth r6, r10, ror #16 1.233 + uxth r10, r10 1.234 + add r6 , r1, r6, lsl #3 1.235 + add r10, r1, r10, lsl #3 1.236 + vst2.32 {d24[0],d25[0]},[r10,:64] 1.237 + vst2.32 {d24[1],d25[1]},[r6,:64] 1.238 + b 1b 1.239 +1: 1.240 + vneg.f32 d7, d7 @ R*s-I*c 1.241 + uxth r12, r6, ror #16 1.242 + uxth r6, r6 1.243 + add r12, r1, r12, lsl #3 1.244 + add r6, r1, r6, lsl #3 1.245 + vst2.32 {d6[0],d7[0]}, [r6,:64] 1.246 + vst2.32 {d6[1],d7[1]}, [r12,:64] 1.247 + uxth r6, r10, ror #16 1.248 + uxth r10, r10 1.249 + add r6 , r1, r6, lsl #3 1.250 + add r10, r1, r10, lsl #3 1.251 + vst2.32 {d24[0],d25[0]},[r10,:64] 1.252 + vst2.32 {d24[1],d25[1]},[r6,:64] 1.253 + 1.254 + mov r4, r0 1.255 + mov r6, r1 1.256 + bl ff_fft_calc_neon 1.257 + 1.258 + mov r12, #1 1.259 + ldr lr, [r4, #28] @ mdct_bits 1.260 + ldr r4, [r4, #32] @ tcos 1.261 + lsl r12, r12, lr @ n = 1 << nbits 1.262 + lsr lr, r12, #3 @ n8 = n >> 3 1.263 + 1.264 + add r4, r4, lr, lsl #3 1.265 + add r6, r6, lr, lsl #3 1.266 + sub r1, r4, #16 1.267 + sub r3, r6, #16 1.268 + 1.269 + mov r7, #-16 1.270 + mov r8, r6 1.271 + mov r0, r3 1.272 + 1.273 + vld2.32 {d0-d1}, [r3,:128], r7 @ d0 =r1,i1 d1 =r0,i0 1.274 + vld2.32 {d20-d21},[r6,:128]! @ d20=r2,i2 d21=r3,i3 1.275 + vld2.32 {d16,d18},[r1,:128], r7 @ c1,c0 s1,s0 1.276 +1: 1.277 + subs lr, lr, #2 1.278 + vmul.f32 d7, d0, d18 @ r1*s1,r0*s0 1.279 + vld2.32 {d17,d19},[r4,:128]! @ c2,c3 s2,s3 1.280 + vmul.f32 d4, d1, d18 @ i1*s1,i0*s0 1.281 + vmul.f32 d5, d21, d19 @ i2*s2,i3*s3 1.282 + vmul.f32 d6, d20, d19 @ r2*s2,r3*s3 1.283 + vmul.f32 d24, d0, d16 @ r1*c1,r0*c0 1.284 + vmul.f32 d25, d20, d17 @ r2*c2,r3*c3 1.285 + vmul.f32 d22, d21, d17 @ i2*c2,i3*c3 1.286 + vmul.f32 d23, d1, d16 @ i1*c1,i0*c0 1.287 + vadd.f32 d4, d4, d24 @ i1*s1+r1*c1,i0*s0+r0*c0 1.288 + vadd.f32 d5, d5, d25 @ i2*s2+r2*c2,i3*s3+r3*c3 1.289 + vsub.f32 d6, d22, d6 @ i2*c2-r2*s2,i3*c3-r3*s3 1.290 + vsub.f32 d7, d23, d7 @ i1*c1-r1*s1,i0*c0-r0*s0 1.291 + vneg.f32 q2, q2 1.292 + beq 1f 1.293 + vld2.32 {d0-d1}, [r3,:128], r7 1.294 + vld2.32 {d20-d21},[r6,:128]! 1.295 + vld2.32 {d16,d18},[r1,:128], r7 @ c1,c0 s1,s0 1.296 + vrev64.32 q3, q3 1.297 + vst2.32 {d4,d6}, [r0,:128], r7 1.298 + vst2.32 {d5,d7}, [r8,:128]! 1.299 + b 1b 1.300 +1: 1.301 + vrev64.32 q3, q3 1.302 + vst2.32 {d4,d6}, [r0,:128] 1.303 + vst2.32 {d5,d7}, [r8,:128] 1.304 + 1.305 + pop {r4-r10,pc} 1.306 +endfunc