nengel@2: /* nengel@2: * Copyright (c) 2008 Siarhei Siamashka nengel@2: * nengel@2: * This file is part of FFmpeg. nengel@2: * nengel@2: * FFmpeg is free software; you can redistribute it and/or nengel@2: * modify it under the terms of the GNU Lesser General Public nengel@2: * License as published by the Free Software Foundation; either nengel@2: * version 2.1 of the License, or (at your option) any later version. nengel@2: * nengel@2: * FFmpeg is distributed in the hope that it will be useful, nengel@2: * but WITHOUT ANY WARRANTY; without even the implied warranty of nengel@2: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU nengel@2: * Lesser General Public License for more details. nengel@2: * nengel@2: * You should have received a copy of the GNU Lesser General Public nengel@2: * License along with FFmpeg; if not, write to the Free Software nengel@2: * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA nengel@2: */ nengel@2: nengel@2: #include "config.h" nengel@2: #include "asm.S" nengel@2: nengel@2: .syntax unified nengel@2: /* nengel@2: * VFP is a floating point coprocessor used in some ARM cores. VFP11 has 1 cycle nengel@2: * throughput for almost all the instructions (except for double precision nengel@2: * arithmetics), but rather high latency. Latency is 4 cycles for loads and 8 cycles nengel@2: * for arithmetic operations. Scheduling code to avoid pipeline stalls is very nengel@2: * important for performance. One more interesting feature is that VFP has nengel@2: * independent load/store and arithmetics pipelines, so it is possible to make nengel@2: * them work simultaneously and get more than 1 operation per cycle. Load/store nengel@2: * pipeline can process 2 single precision floating point values per cycle and nengel@2: * supports bulk loads and stores for large sets of registers. Arithmetic operations nengel@2: * can be done on vectors, which allows to keep the arithmetics pipeline busy, nengel@2: * while the processor may issue and execute other instructions. Detailed nengel@2: * optimization manuals can be found at http://www.arm.com nengel@2: */ nengel@2: nengel@2: /** nengel@2: * ARM VFP optimized implementation of 'vector_fmul_c' function. nengel@2: * Assume that len is a positive number and is multiple of 8 nengel@2: */ nengel@2: @ void ff_vector_fmul_vfp(float *dst, const float *src, int len) nengel@2: function ff_vector_fmul_vfp, export=1 nengel@2: vpush {d8-d15} nengel@2: mov r3, r0 nengel@2: fmrx r12, fpscr nengel@2: orr r12, r12, #(3 << 16) /* set vector size to 4 */ nengel@2: fmxr fpscr, r12 nengel@2: nengel@2: vldmia r3!, {s0-s3} nengel@2: vldmia r1!, {s8-s11} nengel@2: vldmia r3!, {s4-s7} nengel@2: vldmia r1!, {s12-s15} nengel@2: vmul.f32 s8, s0, s8 nengel@2: 1: nengel@2: subs r2, r2, #16 nengel@2: vmul.f32 s12, s4, s12 nengel@2: vldmiage r3!, {s16-s19} nengel@2: vldmiage r1!, {s24-s27} nengel@2: vldmiage r3!, {s20-s23} nengel@2: vldmiage r1!, {s28-s31} nengel@2: vmulge.f32 s24, s16, s24 nengel@2: vstmia r0!, {s8-s11} nengel@2: vstmia r0!, {s12-s15} nengel@2: vmulge.f32 s28, s20, s28 nengel@2: vldmiagt r3!, {s0-s3} nengel@2: vldmiagt r1!, {s8-s11} nengel@2: vldmiagt r3!, {s4-s7} nengel@2: vldmiagt r1!, {s12-s15} nengel@2: vmulge.f32 s8, s0, s8 nengel@2: vstmiage r0!, {s24-s27} nengel@2: vstmiage r0!, {s28-s31} nengel@2: bgt 1b nengel@2: nengel@2: bic r12, r12, #(7 << 16) /* set vector size back to 1 */ nengel@2: fmxr fpscr, r12 nengel@2: vpop {d8-d15} nengel@2: bx lr nengel@2: endfunc nengel@2: nengel@2: /** nengel@2: * ARM VFP optimized implementation of 'vector_fmul_reverse_c' function. nengel@2: * Assume that len is a positive number and is multiple of 8 nengel@2: */ nengel@2: @ void ff_vector_fmul_reverse_vfp(float *dst, const float *src0, nengel@2: @ const float *src1, int len) nengel@2: function ff_vector_fmul_reverse_vfp, export=1 nengel@2: vpush {d8-d15} nengel@2: add r2, r2, r3, lsl #2 nengel@2: vldmdb r2!, {s0-s3} nengel@2: vldmia r1!, {s8-s11} nengel@2: vldmdb r2!, {s4-s7} nengel@2: vldmia r1!, {s12-s15} nengel@2: vmul.f32 s8, s3, s8 nengel@2: vmul.f32 s9, s2, s9 nengel@2: vmul.f32 s10, s1, s10 nengel@2: vmul.f32 s11, s0, s11 nengel@2: 1: nengel@2: subs r3, r3, #16 nengel@2: vldmdbge r2!, {s16-s19} nengel@2: vmul.f32 s12, s7, s12 nengel@2: vldmiage r1!, {s24-s27} nengel@2: vmul.f32 s13, s6, s13 nengel@2: vldmdbge r2!, {s20-s23} nengel@2: vmul.f32 s14, s5, s14 nengel@2: vldmiage r1!, {s28-s31} nengel@2: vmul.f32 s15, s4, s15 nengel@2: vmulge.f32 s24, s19, s24 nengel@2: vldmdbgt r2!, {s0-s3} nengel@2: vmulge.f32 s25, s18, s25 nengel@2: vstmia r0!, {s8-s13} nengel@2: vmulge.f32 s26, s17, s26 nengel@2: vldmiagt r1!, {s8-s11} nengel@2: vmulge.f32 s27, s16, s27 nengel@2: vmulge.f32 s28, s23, s28 nengel@2: vldmdbgt r2!, {s4-s7} nengel@2: vmulge.f32 s29, s22, s29 nengel@2: vstmia r0!, {s14-s15} nengel@2: vmulge.f32 s30, s21, s30 nengel@2: vmulge.f32 s31, s20, s31 nengel@2: vmulge.f32 s8, s3, s8 nengel@2: vldmiagt r1!, {s12-s15} nengel@2: vmulge.f32 s9, s2, s9 nengel@2: vmulge.f32 s10, s1, s10 nengel@2: vstmiage r0!, {s24-s27} nengel@2: vmulge.f32 s11, s0, s11 nengel@2: vstmiage r0!, {s28-s31} nengel@2: bgt 1b nengel@2: nengel@2: vpop {d8-d15} nengel@2: bx lr nengel@2: endfunc nengel@2: nengel@2: #if HAVE_ARMV6 nengel@2: /** nengel@2: * ARM VFP optimized float to int16 conversion. nengel@2: * Assume that len is a positive number and is multiple of 8, destination nengel@2: * buffer is at least 4 bytes aligned (8 bytes alignment is better for nengel@2: * performance), little endian byte sex nengel@2: */ nengel@2: @ void ff_float_to_int16_vfp(int16_t *dst, const float *src, int len) nengel@2: function ff_float_to_int16_vfp, export=1 nengel@2: push {r4-r8,lr} nengel@2: vpush {d8-d11} nengel@2: vldmia r1!, {s16-s23} nengel@2: vcvt.s32.f32 s0, s16 nengel@2: vcvt.s32.f32 s1, s17 nengel@2: vcvt.s32.f32 s2, s18 nengel@2: vcvt.s32.f32 s3, s19 nengel@2: vcvt.s32.f32 s4, s20 nengel@2: vcvt.s32.f32 s5, s21 nengel@2: vcvt.s32.f32 s6, s22 nengel@2: vcvt.s32.f32 s7, s23 nengel@2: 1: nengel@2: subs r2, r2, #8 nengel@2: vmov r3, r4, s0, s1 nengel@2: vmov r5, r6, s2, s3 nengel@2: vmov r7, r8, s4, s5 nengel@2: vmov ip, lr, s6, s7 nengel@2: vldmiagt r1!, {s16-s23} nengel@2: ssat r4, #16, r4 nengel@2: ssat r3, #16, r3 nengel@2: ssat r6, #16, r6 nengel@2: ssat r5, #16, r5 nengel@2: pkhbt r3, r3, r4, lsl #16 nengel@2: pkhbt r4, r5, r6, lsl #16 nengel@2: vcvtgt.s32.f32 s0, s16 nengel@2: vcvtgt.s32.f32 s1, s17 nengel@2: vcvtgt.s32.f32 s2, s18 nengel@2: vcvtgt.s32.f32 s3, s19 nengel@2: vcvtgt.s32.f32 s4, s20 nengel@2: vcvtgt.s32.f32 s5, s21 nengel@2: vcvtgt.s32.f32 s6, s22 nengel@2: vcvtgt.s32.f32 s7, s23 nengel@2: ssat r8, #16, r8 nengel@2: ssat r7, #16, r7 nengel@2: ssat lr, #16, lr nengel@2: ssat ip, #16, ip nengel@2: pkhbt r5, r7, r8, lsl #16 nengel@2: pkhbt r6, ip, lr, lsl #16 nengel@2: stmia r0!, {r3-r6} nengel@2: bgt 1b nengel@2: nengel@2: vpop {d8-d11} nengel@2: pop {r4-r8,pc} nengel@2: endfunc nengel@2: #endif