# HG changeset patch # User Some Random Person # Date 1333900810 25200 # Node ID 254d86cf269de88285e42092ece8eb4d9be86b23 # Parent fdd66fbc940390081097ebe56e68883a14ac5574 Added Future Arch paper, moves stuff around, and some other things.. diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/Future_Architecture/Future_Architecture.tex --- a/0__Papers/Future_Architecture/Future_Architecture.tex Sun Mar 11 09:26:44 2012 -0700 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1183 +0,0 @@ - - -\documentclass[conference]{IEEEtran} -% -\usepackage{makeidx,geometry,amssymb,graphicx,calc,ifthen} -% - -% *** CITATION PACKAGES *** -% -%\usepackage{cite} -% cite.sty was written by Donald Arseneau -% V1.6 and later of IEEEtran pre-defines the format of the cite.sty package -% \cite{} output to follow that of IEEE. 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Basically, -% \url{my_url_here}. - - - - - -% *** Do not adjust lengths that control margins, column widths, etc. *** -% *** Do not use packages that alter fonts (such as pslatex). *** -% There should be no need to do such things with IEEEtran.cls V1.6 and later. -% (Unless specifically asked to do so by the journal or conference you plan -% to submit to, of course. ) - - -% correct bad hyphenation here -\hyphenation{op-tical net-works semi-conduc-tor} - - -\begin{document} -\bibliographystyle{plain} -% - -\title{The Shape of Future Architectures} - -\author -{ - \IEEEauthorblockN{Sean Halle} - \IEEEauthorblockA - { - University of California at Santa Cruz\\ - and INRIA Paris\\ - Email: sean.halle@inria.fr - } - \and - \IEEEauthorblockN{Albert Cohen} - \IEEEauthorblockA - { INRIA Paris\\ - Email: albert.cohen@infria.fr - } -} - - -\maketitle -% - -\begin{abstract} - Process technology is rapidly approaching multiple fundamental physical limits that combine to increase the cost of producing chips faster than the increase in density. Whether or not process technology continues to shrink, the economics will slow the demand for chips from future processes. This will, for the first time, shift the design decisions from being shortest time-to-market towards being the greatest efficiency per transistor -- either in computation delivered towards the goal end-user measurement such as throughput, or in energy per operation. - -The implication for processor architecture is to accelerate the trend away from "easy to program" structures such as out-of-order pipelines and coherent shared memory, and towards hierarchical designs that force application information to be exploited in explicitly managing the placement and movement of data, in order to keep it as local for as much of the computation as possible. The cost of communication will be the dominant factor driving the shape of future architectures, both from a computation-bottleneck cost and an energy per operation cost. - -Integration will be pushed towards the third dimension in order to mitigate the communication costs -- indeed main memories have long been on that path. This approach will hasten the development of 3 dimensional integration processes. The architecture implication is that -\end{abstract} - -\section{Motivation} - -Threads were invented to be virtual sequential processors, but are -problematic when one has multiple physical cores. Not only -are they difficult to use for parallel code, but their parallel performance is poor -because they block the language from controlling -task placement. The language often knows which cores are likely to already -have data in the cache which a new task requires as input. If it had -control, the language could place tasks where the data is likely to already -reside, reducing communication and increasing performance and power -efficiency. A thread replacement is needed that is both easy to use in -applications and gives the language control over task placement. - -The first question is, what is the easiest to use parallelism construct? There -exist many to choose from: Threads (for legacy reasons); Actors -{\cite{Hewitt10}}{\cite{Actors97}}; Components {\cite{ComponentModel00}}; -process calculi {\cite{hoare78}} {\cite{milner99}}; -coordination languages {\cite{Gelernter85Linda}}; and new ones -continually invented. - -We demonstrate in this paper a thread replacement that lets any such parallelism -construct be plugged in. It is the first extensible hardware abstraction, -allowing to plug-in both preferred parallelism constructs and preferred -runtime scheduler. We focus in this introductory paper on -the parallelism construct support, illustrating how to implement synchronous -\texttt{send}-\texttt{receive} constructs motivated by process calculi, -the \texttt{spawn} and \texttt{sync} constructs from Cilk, and even -\texttt{mutex} and \texttt{condition variable} constructs from pthreads. -However, the schedulers we implemented have no -interesting performance optimizations. - -The next question is, how much effort is required to implement a plugin? Our -mechanism protects the plugin from exposure to concurrency issues, allowing -the parallelism constructs to be implemented with sequential algorithms. It -accomplishes this by introducing a ``virtual'' time that sequentializes events -that appear, to the program, to be simultaneous. - -We call our abstraction Virtualized Master-Slave, or VMS. We demonstrate a user-level -implementation in this paper, although it is ideally implemented as the base -hardware abstraction of the OS. - -It involves subtle concepts related to time in the program vs time in the -plugin vs physical time. We explain it in four levels, starting with an abstract definition - and moving down to implementation. - -The first level is the theoretical definition, given in Section \ref{secAbsModel}. Second is the elements -of our implementation and how they relate to the theoretical definition, in Section \ref{secInternal}. -Third is the application code point of view, in Section \ref{secApp}, which is tied back to both -the abstract model and the internal elements. The fourth view, -also in Section \ref{secApp}, shows the implementation of the plugin for a parallel -construct. Additionally, -measurements of effectiveness appear -in Section \ref{secResults} and conclusion is in \ref{secConclusion}. - -\section{Background and Related Work} - -{\bf Side-stepping OS Threads:\ }User-level thread packages and most parallel -language runtimes have to side-step OS threads, by pinning one to each core, -which effectively gives the user-level package control over the core. Our VMS -implementation also does this. We are not claiming in this paper to have the -OS level implementation of VMS that the model is capable of -- just the -user-space version. - -Related work either provides a variation on the Thread model, or is a full -language with included parallelism constructs. For example, - TBB {\cite{TBBHome}} is a user-space thread package with added features. -It allows -tasks to create other tasks and control when to start their -execution. However, one cannot plug in alternate parallelism-control constructs, such as -rendez-vous style send and receive, which would have to be made using locks. - Likewise, Cilk {\cite{CILKHome}} -provides a simpler and easier to use version of TBB's task scheduler, but is -limited to only tree-shaped task graphs. OpenMP {\cite{OpenMPHome}} allows - creating tasks and controlling their execution order, -but is a language, not a hardware abstraction. All of these may -alternatively be implemented via plugins to VMS, with similar performance. - -In contrast, VMS is the first hardware abstraction that doesn't impose its own concurrency -semantics, but rather takes preferred ones as plugins. This makes it not a -language itself, but a {\em{support}} mechanism for language level -parallelism constructs. The parallelism constructs in Actors, Components, -pthreads, and so on may all be implemented as VMS plugins. - -{\bf Virtual Processor (VP) Definition:\ }We want to avoid the confusion -associated with the terms ``thread'' and ``task'' so will use the term -{\em{virtual processor}} (VP), which we define as state in combination with -the ability to animate code or {\em{an additional level of virtual -processors}}. The state consists of a stack with its contents, a program -counter, a pointer to top of stack, and a pointer to the current stack frame. - -\section{Abstract Definition of VMS} -\label{secAbsModel} - -We give an intuitive overview, then add details in the following sub-sections. - -{\bf Intuitive Overview:\ }VMS is concerned primarily with time and -guarantees about it. This is because parallelism constructs control how the -time-lines of different virtual processors intersect. They also guarantee -relations of time lines to hardware events. - -As an example, consider a program that writes into a data structure in one -time-line, then calls a \texttt{send} construct, meanwhile in a different -time-line it calls the \texttt{receive} construct then reads the data -structure. The constructs should guarantee that all data written before the -\texttt{send} is readable in the other time-line after the -\texttt{receive}. VMS provides primitive guarantees, which plugged-in code -builds upon to provide such higher-level guarantees. - -To support parallelism constructs, VMS provides: primitive operations to create and suspend -VPs; a way for plugged-in code to control when each VP is (re)started; and -time-related guarantees. These are enforced on all hardware, be it shared -memory or distributed, with strong memory consistency or weak. - -{\bf Definition in Three Parts:\ }We give the abstract definition in three -parts: a definition of the elements of a VMS computation system; a definition -of time and the key VMS guarantee; and a definition of virtual processor -scheduling states and transitions between them. - -The definition we give is for VMS {\em{with plugins present}}. \ Hence, it -covers the behavior of all possible parallelism constructs implementable with -VMS. The Master mentioned in the definition is an abstract -entity, with a plugin present. In practice, this Master entity is implemented -as part of a core VMS, and plugins later added. This VMS-core is the -hardware abstraction. It hides the physical hardware behind an interface that -creates virtual processors and enforces well-defined time-behavior. - - -\subsection{The Elements of a VMS Computation System} - -\texttt{- }A VMS program has multiple VPs, which are Slaves, -each with an independent time-line. - -\texttt{- }A schedule of Slaves is generated by a Master -entity, from within separate time-line(s). - -\texttt{- }A schedule is defined as the set of points at which -VPs are (re)animated. - -\texttt{- }All semantic parallelism behavior is invoked via -communication with the Master. - -\texttt{- }Communication with the Master happens by using a -model-provided primitive, which causes {\em{voluntary}} suspension of the -program's VP. - - -What is important here is: that the choice of which VP is animated, at which -point, happens in a separate time-line; and that the VPs suspend voluntarily -for each parallelism construct. This means that {\em{scheduling is separated -from the application code}}, the key point. - -The Master entity appears to be a single entity to the slaves, but may be -implemented by multiple Master VPs hidden inside the VMS implementation. - -VPs use the Master as an intermediary to: semantically communicate with each -other; cause creation of new program VPs; and to influence re-animation of -VPs. As a subtlety, notice that hardware mechanisms, such as coherent shared -memory, allow communication to take place that is not visible to the -parallelism constructs. Parallelism constructs must be separately called in -order to make use of shared variable communication safe. - -{\bf Definitions:\ }VMS is intended only for hardware systems that consist of processing elements -connected by communication. We define a memory-space to be a processing -element, albeit without the ability to transform data. We define a -{\em{physical core}} to be a processing element that {\em{does}} transform -data, and require that it execute a sequential stream of instructions. We -define a program-time as the sequence of instructions animated by a Slave VP -(which is eventually animated by a physical core). A Slave VP has associated -{\em{scheduling state}} that, among other things, relates to how its -program-time progresses relative to physical time on the cores. - -\subsection{Time in VMS} - -\texttt{- }VMS has three levels of time: {\em{Program time}}, -{\em{ Master time}}, and {\em{Virtual time}}. - -\texttt{- }Program time is local to a Slave VP, measured in -instruction executions. - -\texttt{- }Master time is hidden from the program and is -independent from all Program times. - -\texttt{- }Virtual time is the ordered set of changes in -scheduling state of Slave VPs. - - - -What is most important here is that Virtual time defines a global sequential -ordering. This ordering is consistent with the key VMS guarantee (given -below), and each point in it is computed within Master time. - -Also, the independence between program times and master time has subtle -advantages. It enables elegant enforcement of the VMS guarantee, and -implementation simplifications that become clear after gaining deep -implementation knowledge. - -In VMS, each event relevant to parallel semantics is tied to a transition of -the state of a Slave VP. This means that implementing the behavior of parallel -semantics is equivalent to controlling the order of transitions of state of -virtual processors. - -{\bf Definitions:\ }The stream of instructions in a given program-time is -broken into a number of {\em{trace-segments}}, separated by suspension -points. Each trace-segment is animated by a single physical core, but not -necessarily the same core as animated the other trace segments. A suspend -point is created by a Slave VP executing the ``suspend'' primitive provided by -VMS. A suspend point has no duration in program time, but has distinct start -and end points in virtual time. The end-suspension points of two different -program times can be tied together within virtual time, which is called a -{\em{tie point}} and has special significance to parallel constructs. The -physical-time of a core has no relationship to any program time, except for -the various time-guarantees in this definition of VMS. - -\begin{figure}[ht] - \includegraphics[width=2.9in]{../figures/Time_in_VMS_1.png} - \caption - {Mapping program time onto Virtual time. \ The - Master controls creation of new program time lines, and ending suspend - points. Here, it has ended two suspend points at a common tie-point. - } -\label{figTimeMapping} -\end{figure} - -{\bf Relating time-lines to each other:\ }Figure \ref{figTimeMapping} -illustrates how trace-segments relate to suspend points, and map onto -virtual time. A trace segment starts in virtual time where suspend is ended, as seen. - In fact, the two trace segments shown have a common -start-point within virtual time. This is because the parallelism semantics -chose to start them at the same point -- this is what a tie -point is. A key note is that the lengths in virtual time have no relation to -the lengths in program-time. The only defined feature is that those two -trace-segments have a common start-point in virtual time. This means that the -two suspend points are considered to be tied together. - -{\bf The Key VMS guarantee:\ }\label{VMSguarantee}Being tied together -means that all physical events that can be observed by both program-times are -covered by the key VMS guarantee: any events triggered before the common -suspend point in one program time are guaranteed visible in the other program -time after the common suspend point. They {\em{might}} be visible before, -but it's not guaranteed. In addition, events triggered after the common -suspend point in one are guaranteed not visible before the common suspend -point in the other. {\em{This two-part guarantee can be considered the heart -of VMS.}} - -Intuitively, a tie-point separates before it from after such that tied program -times agree (illustrated with code in Section \ref{secApp} Figure \ref{figAnimVP}). But the subtlety is -that events triggered before the tie-point, {\em{might}} be visible to the -other before, and ones triggered after {\em{might not}} be visible to the -other after -- physical events triggered before are only guaranteed visible -{\em{after}} the tie point, and events after are only guaranteed -{\em{not}} visible {\em{before}} the tie point. - -This is a form of bounded non-determinism. The pattern of suspension -end-points determines which trace-segments overlap in Virtual time, and events -triggered in one might be visible in overlapped ones. But no guarantees cover -these. If one segment tries to observe, it will see events triggered by -overlapped segments in non-deterministic order. - -The VMS implementation defines which physical events are covered by the key -VMS guarantee (reads/writes, network communication, DMA, I/O). - -{\bf Globally consistent sequential order:\ }VMS maps suspend-start, -suspend-end, and hence tie-points, to a globally-consistent sequential order -in Virtual time. This enables one of VMS's key benefits: sequential -algorithms for parallel constructs. - -Tie points define parallel behavior, so an implementation of how to choose tie -points equals an implementation of parallel constructs. The Master chooses -tie-points, so plugging code to choose tie-points into the Master equals -plugging in parallel constructs. - -\subsection{Scheduling State} - -Scheduling state is used in VMS to organize internal activity, for enforcing -the guarantees. - -\texttt{- }VPs have three scheduling states: {\em{Animated}}, -{\em{Blocked}}, {\em{Ready}} (Figure \ref{figStates}). - -\texttt{- }VPs in Animated are {\em{allowed}} to advance -program-time with {\em{local}} physical time. - -\texttt{- }VPs in Blocked and Ready do not advance their -program-time. - -\texttt{- }Animated has two physical states: -{\em{Progressing}} and {\em{Stalled}}. - -\texttt{- }VPs in Progressing advance program-time with local -physical time, those in Stalled do not (allowing non-semantic suspend). - -\texttt{- }Scheduling states are defined in Virtual time only. - -\texttt{- }Progressing and Stalled are defined in local -physical time only (invisible in Virtual). - - -\begin{figure}[h] - \includegraphics{../figures/Scheduling_states_2.png} - \caption{Scheduling states of a slave VP in the VMS model.} - \label{figStates} -\end{figure} - -Some important points: 1) only VPs Animated can trigger physical events that -are seen in other program time-lines; 2) the distinction between Blocked vs -Stalled is that a VP has to explicitly execute a VMS primitive operation to -enter Blocked, making it part of the semantics of parallelism constructs. In -contrast, Stalled happens invisibly, with no effect on semantic behavior. It -is due to hardware events hidden inside VMS, such as interrupts. - -The Ready state is used to separate the parallelism-construct behavior from -the scheduling behavior. It acts as a ``staging area'' for scheduling. VPs -placed into this state are {\em{allowed}} to be animated, then the scheduler -decides when and where. - -A subtle but illustrative point is that actions {\em{outside}} a given -program time cause the VP to transition Blocked$\rightarrow$Ready, which -contrasts to lock algorithms like spin-locks or Dijkstra's, where the -concurrency-related behavior takes place {\em{inside}} program time. - -{\bf Transition Between Slave Scheduling States:\ } - -\texttt{- }VPs transition states as shown in Figure \ref{figStates}. - -\texttt{- }Animated$\rightarrow$Blocked is caused by a Slave VP -executing the Suspend VMS primitive. - -\texttt{- }Blocked$\rightarrow$Ready is determined by the -semantics implemented in the plugin. - -\texttt{- }Ready$\rightarrow$Animated is determined by the -scheduler in the plugin. - -\texttt{- }Transitions in scheduling state have a globally -consistent order in Virtual time. - - -The parallelism primitives executed by a program do not control change in -scheduling states. They merely communicate messages to the Master, via a VMS -supplied primitive. Inside the Master, the plugin's parallelism construct -implementation processes the message. Based on that, it performs changes in -state from Blocked$\rightarrow$Ready, creates new VPs, and dissipates existing -VPs. Most communication from Slave to Master requires the VP to suspend when -it sends the message. A few messages, like creating new Slave may be sent -without suspending. - -The suspend primitive decouples local physical time from Virtual time. -Execution causes immediate transition to Stalled in physical time, then the -Master performs Animated$\rightarrow$Blocked, fixing that transition in -Virtual time. The only relationship is causality. This weak relation is what -allows suspension-points to be serialized in Virtual time, which in turn is -what allows using sequential algorithms to implement parallelism constructs. - - -\subsection{Plugins} - -\begin{figure}[ht] - \includegraphics{../figures/VMS-core__plugins.png} - \caption - { - The Master has been split into a generic core and a language-specific plug-in. - The core encapsulates the hardware and remains the same across applications. - The plug-in is part of the parallelism-construct implementation. It is - loaded separately onto the hardware and linked to the application when run. - } - \label{figMasterSplit} -\end{figure} - - -The Master entity has two parts, a generic core part and a plugin (Figure \ref{figMasterSplit}). - The core part of the Master is implemented as part of -VMS-core. The plug-in supplies two functions: the communication-handler and -the scheduler, both having a standard prototype. The communication-handler -implements the parallelism constructs, while scheduler assigns VPs to cores. - -An {\em{instance}} of a plugin is created as part of initializing an -application, and the instance holds the semantic and scheduling state for that -run of the application. This state, combined with the virtual processor states -of the slaves created during that application run, represents progress of the -work of the application. \ For example, multi-tasking is performed simply by -the Master switching among plug-in instances when it has a resource to offer -to a scheduler. The parallelism-semantic state holds all information needed to -resume (hardware state, such as TLB and cache-tags is inside VMS-core). - - - -\section{Internal Workings of Our Implementation} -\label{secInternal} - -We name the elements of our example implementation and describe their logical -function, then relate them to the abstract model. We then step through the -operation of the elements. - -{\bf Elements and Their Logical Function:\ }As illustrated in Figure \ref{figInternals}, -our VMS implementation is organized around physical cores. - Each core has its own {\em{master -virtual-processor}}, \texttt{masterVP}, and a {\em{physical-core controller}}, which communicate via a set of -scheduling slots, \texttt{schedSlot}. The Master in the abstract definition -is implemented by the multiple \texttt{masterVP}s plus a particular plugin -instance with its shared parallelism-semantic state (seen at the top). - -On a given core, only one of: the core-controller, \texttt{masterVP}, or a -slave VP, is animated at any point in local physical time. Each -\texttt{masterVP} animates the same function, called -\texttt{master\_loop}, and each slave VP animates a function from the -application, starting with the top-level function the slave is created with, -and following its call sequence. The core controller is implemented here as a -Linux pthread that runs the \texttt{core\_loop} function. - -Switching between VPs is done by executing a VMS primitive that suspends the -VP. This switches the physical core over to the controller, by jumping to the -start of the \texttt{core\_loop} function, which chooses the next VP and -switches to that (switching is detailed in Section \ref{secApp} Figure \ref{figAssembly}). - -{\bf Relation to Abstract Model:\ }We chose to implement the Master entity -of the model by a set of \texttt{masterVP}s, plus plug-in functions and -shared parallelism-semantic state. What we call VMS-core consists of this -implementation of the Master, plus the core-controllers, plus the VMS -primitive libraries, for creating new VPs and dissipating existing VPs, suspending VPs, -and communicating from slave VP to Master. In Figure \ref{figInternals}, -everything in green is part of VMS-core, while the plugin is in red, and -application code appears as blue, inside the slave VP. - -Virtual time in the model is implemented via a combination of four things: a -\texttt{masterLock} (not shown) that guarantees non-overlap of -\texttt{masterVP} trace-segments; the \texttt{master\_loop} which performs -transition Animated$\rightarrow$Blocked; the \texttt{comm\_handler\_fn} -which performs Blocked$\rightarrow$Ready and the \texttt{scheduler\_fn} -which performs Ready$\rightarrow$Animated. \ Each state transition is one step -of Virtual time; is guaranteed sequential by the non-overlap of -\texttt{masterVP} trace segments; and is global due to being in -parallelism-semantic state that is shared (top of Figure \ref{figInternals}). - -Transitions Progressing$\rightleftarrows$Stalled within the Animated state are -invisible to the parallelism semantics, the Master, and Virtual time, and so -have no effect on the elements seen. - - -\begin{figure*}[!t] - \includegraphics[width=5in]{../figures/VMS-core__internal_workings.png} - \caption - { Internal elements of our example VMS implementation - } - \label{figInternals} -\end{figure*} - -{\bf Steps of Operation:\ }The steps of operation are numbered, in Figure \ref{figInternals}. - Taking them in order, 1) \texttt{master\_loop} scans -the scheduling slots to see which ones' slaves have suspended since the -previous scan. \ 2) It hands these to the \texttt{comm\_handler\_fn} plugged -in (which equals transition Animated$\rightarrow$Blocked). \ 3) The VP has a -request attached, and data in it causes \ the \texttt{comm\_handler\_fn} -to manipulate data structures in the shared parallelism-semantic state. \ -These structures hold all the slaves in the blocked state (code-level detail -in Figure \ref{figReqHdlr}, Section \ref{secApp}). \ 4) Some requests cause slaves to be moved to a -\texttt{readyQ} on one of the cores (Blocked$\rightarrow$Ready). Which -core's \texttt{readyQ} receives the slave is under plugin control, -determined by a combination of request contents, semantic state and physical -machine state. 5) During the scan, the \texttt{master\_loop} also looks for -empty slots, and for each calls the \texttt{scheduler\_fn} plugged in. It -chooses a slave from the \texttt{readyQ} on the core animating -\texttt{master\_loop}. \ 6) The \texttt{master\_loop} then places the -slave VP's pointer into the scheduling slot (Ready$\rightarrow$Animated), -making it available to the \texttt{core\_loop}. 7) When done with the scan, -\texttt{masterVP} suspends, switching animation back to the -\texttt{core\_loop}. \ 8) \texttt{core\_loop} takes slave VPs out of the -slots, then 9) switches animation to them. \ 10) When a slave self-suspends, -animation returns to the \texttt{core\_loop} (detail in code in Figure 9), -which picks another, until 11) all slots are empty and the -\texttt{core\_loop} switches animation to the \texttt{masterVP}. - -{\bf Enabling sequential implementation of parallelism semantics:\ }All of -that happens on each core separately, but in this particular implementation we -use a central \texttt{masterLock} to ensure that only one core's -\texttt{masterVP} can be active at any time. This guarantees non-overlap -of trace-segments from different \texttt{masterVP}s, allowing the plugins to -use sequential algorithms, without a performance penalty, as verified in -Section \ref{secResults}. - -Relating this to the abstract model: the parallelism-semantic behavior of the -Master is implemented by the communication handler, in the plugin. It thus -runs in the Master time referred to, in the model, in Section \ref{secAbsModel}. Requests are -sent to the Master by self-suspension of the slaves, but sit idle until the -other slaves in the scheduling slots have also run. This is the passive -behavior of requests that was noted in Section \ref{secAbsModel}, which allows the -\texttt{masterVP}s to remain suspended until needed. This in turn enables -the \texttt{masterVP}s from different cores to be non-overlapped. It is the -non-overlap that enables the algorithms for the parallelism semantics to be -sequential. - - - - -\section{Code Level View} -\label{secApp} - -To relate the abstract model and the internal elements to application code and -parallelism-library code, we give code snippets that illustrate key features. - We start with the application then work down through the sequence of calls, -to the plugin, using our SSR {\cite{VMSHome}} parallelism-library as an -example. - -In general, applications are either written in terms of a full custom language -that has its own syntax, or a base language with a parallelism library, which -is often called an {\em{embedded language}}. Our demonstrators, VCilk -{\cite{VMSHome}}, Vthread, and SSR, are all parallelism libraries. A full -custom language would follow the standard practice of performing -source-to-source transform, from custom syntax into C plus parallelism-library -calls. - -{\bf SSR:\ }SSR stands for Synchronous Send-Receive, and details of its -calls and internal implementation will be given throughout this section. It -has two types of construct. The first, called {\em{from-to}} has two calls: -\texttt{SSR\_send\_from\_to} and \texttt{SSR\_receive\_from\_to}, both of -which specify the sending VP as well as the receiving VP. \ The other, called -{\em{of-type}} also has two calls: \texttt{SSR\_\_send\_of\_type\_to} and -\texttt{SSR\_\_receive\_of\_type}, which allow a receiver to accept from -anonymous senders, but select according to type of message. - - -% An example of a double column floating figure using two subfigures. -% (The subfig.sty package must be loaded for this to work.) -% The subfigure \label commands are set within each subfloat command, the -% \label for the overall figure must come after \caption. -% \hfil must be used as a separator to get equal spacing. -% The subfigure.sty package works much the same way, except \subfigure is -% used instead of \subfloat. -% -%\begin{figure*}[!t] -%\centerline{\subfloat[Case I]\includegraphics[width=2.5in]{subfigcase1}% -%\label{fig_first_case}} -%\hfil -%\subfloat[Case II]{\includegraphics[width=2.5in]{subfigcase2}% -%\label{fig_second_case}}} -%\caption{Simulation results} -%\label{fig_sim} -%\end{figure*} -% -% Note that often IEEE papers with subfigures do not employ subfigure -% captions (using the optional argument to \subfloat), but instead will -% reference/describe all of them (a), (b), etc., within the main caption. - - -{\bf Application View:\ } Figure \ref{figAnimVP} shows snippets of application code, which use the SSR parallelism -library. The most important feature is that all calls take a pointer to the -VP that is animating the call. This is seen at the top of the figure where slave VP creation takes a pointer -to the VP asking for creation. Below that is the standard prototype for top level functions, -showing that the function receives a pointer to the VP it is the top level function for. - -The pointer is placed on the stack by VMS when it creates the VP, and is the means by -which the application comes into possession of the pointer. This animating VP is -passed to all library calls made from there. For example, the bottom shows a pointer to the -animating VP placed in the position of sender in -the \texttt{send} construct call. Correspondingly, for the \texttt{receive} construct, -the position of receiving VP is filled by the VP animating the call. - -\begin{figure}[ht] -{\noindent -{\scriptsize -{\small Creating a new processor:} - \begin{verbatim} -newProcessor = SSR__create_procr( &top_VP_fn, - paramsPtr, animatingVP ); \end{verbatim} - -{\small prototype for the top level function:} - \begin{verbatim} -top_VP_fn( void *parameterStrucPtr, VirtProcr - *animatingVP ); \end{verbatim} - -{\small handing animating VP to parallelism constructs:} - \begin{verbatim} -SSR__send_from_to( messagePtr, animatingVP, - receivingVP ); -messagePtr = SSR__receive_from_to( sendingVP, - animatingVP ); \end{verbatim} -} -} -\caption -{ -Application code snippets showing that all calls to the parallelism library -take the VP animating that call as a parameter. -} -\label{figAnimVP} -\end{figure} - -Relating these to the internal elements of our implementation, the - \texttt{animatingVP} suspends inside each of these -calls, passing a request (generated in the library) to one of the \texttt{masterVP}s. - The \texttt{masterVP} then calls the \texttt{comm-handler} - plugin, and so on, as described in Section \ref{secInternal}. - -For the \texttt{SSR\_\_create\_processor} call, the comm-handler - in turn calls a VMS primitive to perform the creation. - The primitive places a pointer to the newly created VP onto its stack, so that when -\texttt{top\_VP\_fn} is later animated, it sees the VP-pointer as a -parameter passed to it. \ All -application code is either such a top-level function, or has one at the root -of the call-stack. - -The send and receive calls both suspend their animating VP. When both have -been called, the communication handler pairs them up and resumes both. This -ties time-lines together, invoking the VMS guarantee. Both -application-functions know, because of the VMS guarantee (Section \ref{secAbsModel}), that -writes to shared variables made before the send call by the sender are visible -to the receiver after the receive call. This is the programmer's view of tying -together the local time-lines of two different VPs, as defined in Section \ref{secAbsModel}. - - -{\bf Concurrency-Library View:\ }A parallelism library function, in -general, only creates a request, sends it, and returns, as seen below. To -send a request, it uses the combined request-and-suspend VMS primitive that -attaches the request then suspends the VP. The primitive requires the -pointer to the VP, to attach the request and to suspend it. - - -\begin{figure}[ht] -{\noindent -{\scriptsize - \begin{verbatim} -void * SSR__receive_from_to( VirtProcr *sendVP, - VirtProcr *receiveVP ) - { SSRSemReq reqData; - reqData.receiveVP = receiveVP; - reqData.sendVP = sendVP; - reqData.reqType = receive_from_to; - VMS__send_sem_request( &reqData, receiveVP ); - return receiveVP->dataReturnedFromRequest; - } \end{verbatim} -} -} -\caption{Implementation of SSR's receive\_from\_to library function.} -\label{figImplLib} -\end{figure} - - -In Figure \ref{figImplLib}, notice that the request's data is on the stack of the virtual -processor that's animating the call, which is the \texttt{receiveVP}. The -\texttt{VMS\_\_send\_sem\_request} suspends this VP, which changes the -physical core's stack pointer to a different stack. So the request data is -guaranteed to remain undisturbed while the VP is suspended. - -Figure \ref{figAssembly} shows the implementation of the VMS suspend primitive. As seen in -Figure \ref{figInternals}, suspending the \texttt{receiveVP} involves -switching to the \texttt{core\_loop}. In our implementation, this is done by -switching to the stack of the pthread pinned to the physical core and then -jumping to the start-point of \texttt{core\_loop}. - -This code uses standard techniques commonly employed in co-routine -implementations. Tuning effort spent in \texttt{core\_loop} is inherited by -all applications. - - -\begin{figure}[ht] -{\noindent -{\scriptsize - \begin{verbatim} -VMS__suspend_procr( VirtProcr *animatingVP ) - { animatingVP->resumeInstrAddr = &&ResumePt; - //GCC takes addr of label - animatingVP->schedSlotAssignedTo-> - isNewlySuspended = TRUE; - //for master_loop to see - - - - ResumePt: - return; - } \end{verbatim} -} -} - \caption -{Implementation of VMS suspend processor. -Re-animating the virtual processor reverses this sequence. \ It saves the -\texttt{core\_loop}'s resume instr-addr and stack ptr into the VP structure, -then loads the VP's stack ptr and jmps to its \texttt{resumeInstrAddr}. -} -\label{figAssembly} -\end{figure} - - -{\bf Plugin View:\ }SSR's communication handler dispatches on the -\texttt{reqType} field of the request data, as set by the -\texttt{SSR\_\_receive\_from\_to} code. It calls the handler code in -Figure \ref{figReqHdlr}. This constructs a hash-key, by concatenating the from-VP's pointer -with the to-VP's pointer. Then it looks-up that key in the hash-table that SSR uses -to match sends with receives, which is in the shared semantic state seen at -the top of Figure \ref{figInternals} in Section \ref{secInternal}. - -The most important feature in Figure \ref{figReqHdlr} is that both send and receive -will construct the same key, so will find the same -hash entry. Whichever request is handled first in Virtual time will see the -hash entry empty, and save itself in that entry. The second to arrive -sees the waiting request and then resumes both VPs, by putting them into their -\texttt{readyQ}s. - -Access to the shared hash -table can be considered private, as in a sequential algorithm. This is because - our VMS-core implementation ensures that only -one handler on one core is executing at a time. - - -\begin{figure}[ht] -{\noindent -{\scriptsize - \begin{verbatim} -handle_receive_from_to( VirtProcr *requestingVP, - SSRSemReq *reqData, SSRSemEnv *semEnv ) - { commHashTbl = semEnv->communicatingVPHashTable; - key[0] = reqData->receiveVP; key[1] = - reqData->sendVP; //send uses same key - waitingReqData = lookup_and_remove( key, - commHashTbl ); //get waiting request - if( waitingReqData != NULL ) - { resume_virt_procr( waitingReqData->sendVP ); - resume_virt_procr( waitingReqData-> - receiveVP ); - } - else - insert( key, reqData, commHashTbl ); - //receive is first to arrive, make it wait - } \end{verbatim} -} -} - \caption -{Pseudo-code of communication-handler for -\texttt{receive\_from\_to} request type. The \texttt{semEnv} is a pointer -to the shared parallelism-semantic state seen at the top of Figure -\ref{figInternals}. -} -\label{figReqHdlr} -\end{figure} - - - - -\section{Results} -\label{secResults} - -{\bf Setup:\ }We implemented blocked dense matrix multiply with right -sub-matrices copied to transposed form. We ran on a 1 socket by 4 core -Core2Quad 2.4Ghz chip. - -{\bf Implementation-Time:\ }As shown in Table 1, time to implement the -three parallel libraries averages 2 days each. As an example of productivity, -adding nested transactions, parallel singleton, and atomic function-execution -to SSR required a single afternoon, totaling less than 100 lines of C code. - - -\begin{table}[ht] -\caption -{Person-days to design, code, and - test each parallelism library. L.O.C. is lines of (original) C code, excluding libraries and - comments. -} -\label{tabPersonDaysLang} -\begin{center} -\begin{tabular}{llll} - & SSR & Vthread & VCilk\\ - Design & 4 & 1 & 0.5\\ - Code & 2 & 0.5 & 0.5\\ - Test & 1 & 0.5 & 0.5\\ - L.O.C. & 470 & 290 & 310 - \end{tabular} -\end{center} -\end{table} - - -{\bf Execution Performance:\ }Performance of VMS is seen in Table -\ref{tabOverheadCycles}. The code is not optimized, but rather written -to be easy to understand and modify. The majority of the plugin time -is lost to cache misses because the shared parallelism-semantic state moves -between cores on a majority of accesses. Acquisition of the master lock is slow due to the hardware -implementing the CAS instruction. - -Existing techniques will likely improve performance, such -as localizing semantic data to cores, splitting malloc across the cores, -pre-allocating slabs that are recycled, and pre-fetching. However, in many cases, several hundred -nano-seconds per task is as optimal as the applications can benefit from. - -\begin{table}[ht] -\caption -{Cycles of overhead, per scheduled - slave. ``comp only'' is perfect memory, ``comp + mem'' is actual cycles. - ``Plugin-concur'' only concurrency requests, ``plugin-all'' includes - create and malloc requests. Two significant digits due to variability. -} -\label{tabOverheadCycles} -\begin{center} -\begin{tabular}{|l|ll|r|r|} -\hline - & & comp & comp\\ - & & only & +mem\\ - VMS Only & \texttt{master\_loop} & 91 & \ 110\\ - & switch VPs & 77 & \ 130\\ - & (malloc) & 160 & 2300\\ - & (create VP) & 540 & 3800\\ -\hline - Language: & & & \\ - SSR & plugin -- concur & 190 & 540\\ - & plugin -- all & 530 & 2200\\ - & lock & & 250\\ - Vthread & plugin -- concur & 66 & 710\\ - & plugin -- all & 180 & 1500\\ - & lock & & 250\\ - VCilk & plugin -- concur & 65 & 260\\ - & plugin -- all & 330 & 1800\\ - & lock & & 250\\ -\hline -\end{tabular} -\end{center} -\end{table} - - - -{\bf Head to Head:\ }We -compare our implementation of the \texttt{spawn} and \texttt{sync} -constructs against Cilk 5.4, on the top in Table -\ref{tabHeadToHead}, which shows that the same application code has similar -performance. For large matrices, Cilk 5.4's better use of the memory hierarchy -achieves 23\% better performance. However, for small matrices, VCilk is better, - with a factor 2 lower overhead. Cilk 5.4 does not allow controlling the number of spawn events it -actually executes, and chooses to run smaller matrices sequentially, limiting -our comparison. - -When comparing to pthreads, our VMS based implementation has more than an -order of magnitude better overhead per invocation of mutex or condition -variable functionality, as seen on the bottom of Table \ref{tabHeadToHead}. -Applications that inherently have short trace segments will synchronize often -and benefit the most from Vthread. - - - -\begin{table}[ht] -\caption -{On top, exe time in seconds for MM. Below, overhead for pthread vs Vthread. First column is cycles - for perfect memory and second is total measured cycles. pthread cycles are - deduced from round-trip experiments. -} -\label{tabHeadToHead} -\begin{center} -\begin{tabular}{|l@{\ }|@{\ }lr|} -\hline -\rule{0pt}{12pt} - Matrix size&Lang.&sec.\\ -[2pt]\hline - 81x81 & Cilk & 0.017\\ - & VCilk & 0.008\\ -\hline - 324x324 & Cilk & 0.13\\ - & VCilk & 0.13\\ -\hline - 648x648 & Cilk & 0.71\\ - & VCilk & 0.85\\ -\hline - 1296x1296 & Cilk & 4.8\\ - & VCilk & 6.2 \\ -[2pt]\hline -\end{tabular} -\begin{tabular}{c} -\begin{tabular}{|l|rr|r|r|} -\hline - operation & \multicolumn{2}{c|}{Vthread} & pthread & ratio\\ -\hline - & comp & total & & \\ - & only & & & \\ -[2pt]\hline - mutex\_lock & 85 & 1050 & 50,000 & 48:1\\ - mutex\_unlock & 85 & 610 & 45,000 & 74:1\\ - cond\_wait & 85 & 850 & 60,000 & 71:1\\ - cond\_signal & 90 & 650 & 60,000 & 92:1\\ -\hline -\end{tabular}\\ -\end{tabular} -\end{center} -\end{table} - -\section{Conclusion}\label{secConclusion} - -We have shown an alternative to the Thread model that enables easier-to-use -parallelism constructs by splitting -the scheduler open, to accept new parallelism constructs in the form of -plugins. This gives the language control over assigning virtual -processors to physical cores, for performance, debugging, and flexibility -benefits. Parallelism constructs of languages are implementable using -sequential algorithms, within a matter of days, while maintaining low run-time -overhead, on the order of a few hundred nano-seconds per concurrency -operation. - -\bibliography{Bib_for_papers} - -\end{document} diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/Future_Architecture/figures/Separate_comm_processors.eps --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Future_Architecture/figures/Separate_comm_processors.eps Sun Apr 08 09:00:10 2012 -0700 @@ -0,0 +1,619 @@ +%!PS-Adobe-3.0 EPSF-3.0 +%%Creator: cairo 1.8.8 (http://cairographics.org) +%%CreationDate: Sun Apr 08 07:02:01 2012 +%%Pages: 1 +%%BoundingBox: 0 0 253 124 +%%DocumentData: Clean7Bit +%%LanguageLevel: 2 +%%EndComments +%%BeginProlog +/cairo_eps_state save def +/dict_count countdictstack def +/op_count count 1 sub def +userdict begin +/q { gsave } bind def +/Q { grestore } bind def +/cm { 6 array astore concat } bind def +/w { setlinewidth } bind def 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sub {end} repeat +cairo_eps_state restore +%%EOF diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/Future_Architecture/figures/Substitute_instr_with_firm-ware.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Future_Architecture/figures/Substitute_instr_with_firm-ware.svg Sun Apr 08 09:00:10 2012 -0700 @@ -0,0 +1,1133 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + Language Runtime as Firm-ware + + + + Execute + + + + Write Back + + + + Reg + + + + Decode + + + + Fetch + + + + FirmwareFetch + + + + + + + + + runtimeaccelerator + + + + + diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/Future_Architecture/latex/Future_Architecture.aux --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Future_Architecture/latex/Future_Architecture.aux Sun Apr 08 09:00:10 2012 -0700 @@ -0,0 +1,30 @@ +\relax +\bibstyle{plain} +\@writefile{toc}{\contentsline {section}{\numberline {I}What parallel abstractions should the hardware provide?}{1}} +\@writefile{lof}{\contentsline {figure}{\numberline {1}{\ignorespaces A special op-code is recognized by the decode stage, and triggers fetch of instructions from firm-ware. The firm-ware instrs are provided to the OS as a ``hardware driver", and implement the runtime behavior of a language. The application communicates to the runtime by placing pointers to data-structures into registers just before executing the ``switch to runtime" instruction, which starts the fetch from firm-ware. Helper instructions accelerate common runtime operations, such as hash-table lookups, communication, search-for-optimum, and so on. }}{1}} +\newlabel{figTimeMapping}{{1}{1}} +\@writefile{toc}{\contentsline {subsection}{\numberline {\unhbox \voidb@x \hbox {I-A}}Communications via firm-ware}{2}} +\@writefile{toc}{\contentsline {subsection}{\numberline {\unhbox \voidb@x \hbox {I-B}}Communication via separate helper processors}{2}} +\@writefile{lof}{\contentsline {figure}{\numberline {2}{\ignorespaces Communication is performed between local memory and remote memories via a separate communication processor. This processor executes firm-ware that is loaded under OS control. For example, it may implement a software-cache or be scatter-gather code extracted from the application. }}{2}} +\newlabel{figCommProcr}{{2}{2}} +\@writefile{toc}{\contentsline {subsection}{\numberline {\unhbox \voidb@x \hbox {I-C}}Speculation and Fast Control Message Support}{2}} +\@writefile{lof}{\contentsline {figure}{\numberline {3}{\ignorespaces }}{2}} +\newlabel{figSpecHW}{{3}{2}} +\@writefile{toc}{\contentsline {subsection}{\numberline {\unhbox \voidb@x \hbox {I-D}}Example}{3}} +\@writefile{toc}{\contentsline {paragraph}{\numberline {\unhbox \voidb@x \hbox {I-D}0a}setup and switch}{3}} +\@writefile{toc}{\contentsline {paragraph}{\numberline {\unhbox \voidb@x \hbox {I-D}0b}runtime internals}{3}} +\@writefile{toc}{\contentsline {section}{\numberline {II}Which should be the responsibility / functionality of the programmer, the runtime software, and the hardware?}{3}} +\@writefile{toc}{\contentsline {section}{\numberline {III}Specific Topics of Interest}{3}} +\@writefile{toc}{\contentsline {paragraph}{\numberline {\unhbox \voidb@x \hbox {III-}0c}enabling future parallel programming models}{4}} +\@writefile{toc}{\contentsline {paragraph}{\numberline {\unhbox \voidb@x \hbox {III-}0d}innovative architectural execution models}{4}} +\@writefile{toc}{\contentsline {paragraph}{\numberline {\unhbox \voidb@x \hbox {III-}0e}novel memory hierarchies}{4}} +\@writefile{toc}{\contentsline {paragraph}{\numberline {\unhbox \voidb@x \hbox {III-}0f}simplified and scalable memory models}{4}} +\@writefile{toc}{\contentsline {paragraph}{\numberline {\unhbox \voidb@x \hbox {III-}0g}high-level constructs for on-chip communications}{4}} +\@writefile{toc}{\contentsline {paragraph}{\numberline {\unhbox \voidb@x \hbox {III-}0h}characterization of the runtime overheads of parallel applications}{4}} +\@writefile{toc}{\contentsline {paragraph}{\numberline {\unhbox \voidb@x \hbox {III-}0i}future directions in programming massively parallel systems}{4}} +\@writefile{toc}{\contentsline {paragraph}{\numberline {\unhbox \voidb@x \hbox {III-}0j}potential bottlenecks for future parallel systems}{4}} +\@writefile{toc}{\contentsline {section}{\numberline {IV}Conclusion}{5}} +\newlabel{secConclusion}{{IV}{5}} +\bibdata{Bib_for_papers} +\@writefile{toc}{\contentsline {section}{References}{6}} + diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/Future_Architecture/latex/Future_Architecture.bbl --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Future_Architecture/latex/Future_Architecture.bbl Sun Apr 08 09:00:10 2012 -0700 @@ -0,0 +1,3 @@ +\begin{thebibliography}{} + +\end{thebibliography} diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/Future_Architecture/latex/Future_Architecture.blg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Future_Architecture/latex/Future_Architecture.blg Sun Apr 08 09:00:10 2012 -0700 @@ -0,0 +1,22 @@ +This is 8-bit Big BibTeX version 0.99c +Implementation: WIN32 Console, BaKoMa TNS bound. +Release version: 3.71 (18 Aug 1996) + +The top-level auxiliary file: Future_Architecture.aux +The style file: plain.bst +I couldn't open database file Bib_for_papers.bib +---line 28 of file Future_Architecture.aux + : \bibdata{Bib_for_papers + : } +I'm skipping whatever remains of this command +I found no \citation commands---while reading file Future_Architecture.aux +I found no database files---while reading file Future_Architecture.aux + +Here's how much of BibTeX's memory you used: + Cites: 0 out of 7500 + Fields: 125000 out of 125000 + Hash table: 34852 out of 35000 + Strings: 495 out of 30000 + String pool: 4008 out of 750000 + Wizard functions: 2118 out of 10000 +(There were 3 error messages) diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/Future_Architecture/latex/Future_Architecture.tex --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Future_Architecture/latex/Future_Architecture.tex Sun Apr 08 09:00:10 2012 -0700 @@ -0,0 +1,573 @@ +% + + +\documentclass[conference]{IEEEtran} +% +%\usepackage{makeidx,geometry,amssymb,graphicx,calc,ifthen} +\usepackage{amssymb,graphicx,calc,ifthen} +% + +% *** CITATION PACKAGES *** +% +%\usepackage{cite} +% cite.sty was written by Donald Arseneau +% V1.6 and later of IEEEtran pre-defines the format of the cite.sty package +% \cite{} output to follow that of IEEE. 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Be sure and use +% version 4.0 (2003-05-27) and later if using hyperref.sty. cite.sty does +% not currently provide for hyperlinked citations. +% The latest version can be obtained at: +% http://www.ctan.org/tex-archive/macros/latex/contrib/cite/ +% The documentation is contained in the cite.sty file itself. + + + + + + +% *** GRAPHICS RELATED PACKAGES *** +% +\ifCLASSINFOpdf + % \usepackage[pdftex]{graphicx} + % declare the path(s) where your graphic files are + % \graphicspath{{../pdf/}{../jpeg/}} + % and their extensions so you won't have to specify these with + % every instance of \includegraphics + % \DeclareGraphicsExtensions{.pdf,.jpeg,.png} +\else + % or other class option (dvipsone, dvipdf, if not using dvips). graphicx + % will default to the driver specified in the system graphics.cfg if no + % driver is specified. + % \usepackage[dvips]{graphicx} + % declare the path(s) where your graphic files are + % \graphicspath{{../eps/}} + % and their extensions so you won't have to specify these with + % every instance of \includegraphics + % \DeclareGraphicsExtensions{.eps} +\fi +% graphicx was written by David Carlisle and Sebastian Rahtz. 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Basically, +% \url{my_url_here}. + + + + + +% *** Do not adjust lengths that control margins, column widths, etc. *** +% *** Do not use packages that alter fonts (such as pslatex). *** +% There should be no need to do such things with IEEEtran.cls V1.6 and later. +% (Unless specifically asked to do so by the journal or conference you plan +% to submit to, of course. ) + + +% correct bad hyphenation here +\hyphenation{op-tical net-works semi-conduc-tor} + + +\begin{document} + +\bibliographystyle{plain} +% + +\title{Position: Support Runtimes in Hardware,\\ Rather than Specific Parallelism Constructs} + +\author +{ + \IEEEauthorblockN{Sean Halle} + \IEEEauthorblockA + { + Open Source Research Institute\\ + Email: sean.halle@osri.org + } +} + + +\maketitle +% + +\begin{abstract} +This is a position paper, whose purpose is to provide food for thought and a starting point for debate. Although, the ideas are extrapolations from published work on runtime systems and hardware abstractions that have been implemented and successfully demonstrated. + +The main premise is that no parallelism constructs should be directly implemented in hardware, but rather separated into a new category of \emph{firmware} that is tightly integrated into the processor pipeline and managed by the OS. We describe hardware structures that allow traditional thread constructs, domain-specific constructs, transactional memory, and even consistency models be implemented with extremely low overhead, as well as cooperatively engage the language's runtime into pipeline-level hardware-resource management. + +We further take the position that software should be organized into a stack, based around \emph{specialization} of source to target hardware. Each layer of the stack has a role in the specialization process, which spans the lifetime of application code as it goes through the stages of, development, transformation to hardware-specific form, installation, and execution. Hence, specialization includes the toolchain, hand-tuning, auto-tuners, multi-kernels, profiling, and binary optimization. We describe infrastructure to encapsulate and organize these. +\end{abstract} + + + +\section{What parallel abstractions should the hardware provide?} + +Our position is that the hardware should not directly supply any parallel abstractions. Instead, it should supply a mechanism that elevates the language runtime to the status of a Hardware Abstraction Layer, which is separate from the executable and separate from the OS. Thus, parallel abstractions are implemented as soft-extensions to the hardware. With suitable support, many firmware-implemented parallel abstractions would require only a handful of instructions with a similarly low number of cycles of overhead. + + +\begin{figure}[ht] + \center{ + \includegraphics[width=3in, height=2in]{../figures/Substitute_instr_with_firm-ware.eps} + } + \caption + {A special op-code is recognized by the decode stage, and triggers fetch of instructions from firm-ware. The firm-ware instrs are provided to the OS as a ``hardware driver", and implement the runtime behavior of a language. The application communicates to the runtime by placing pointers to data-structures into registers just before executing the ``switch to runtime" instruction, which starts the fetch from firm-ware. Helper instructions accelerate common runtime operations, such as hash-table lookups, communication, search-for-optimum, and so on. + } +\label{figTimeMapping} +\end{figure} + + +Precedence for such soft-extensions to instruction sets exists. The Alpha chips from DEC provided firmware that implemented complex VAX instructions this way. A VAX ``firmware" instruction was executed by switching fetch over to a special memory that contained normal Alpha instructions, which implemented the functionality of the VAX instruction. + +An analogous approach is illustrated in Figure \ref{figTimeMapping}. Here, one op-code is set aside as the ``invoke runtime" operation. Its execution causes instructions to switch to fetching from the firm-ware. Information is communicated via register contents, which point to data-structures that include a hardware defined portion and a language defined portion. + +This firmware was written by the language-provider, so it is separate from the executable. It implements the behavior of parallelism constructs of the language. + +Such an approach addresses security, portability, and efficiency. It is secure because the OS controls the firm-ware. It is portable because the executable only contains the \emph{interface} to the constructs (implementation is separate). It is efficient because the firm-ware runs in user-space, and switching to it costs the same as a \texttt{call} . This also improves application performance, if the hardware gives the firm-ware control over low-level behaviors such as hardware-supported swapping of contexts and control of hybrid cache/scratchpad memory. + +An important feature is that application information can directly affect hardware-level scheduling, communication, and other resource management. This is because the runtime has hardware control and receives application information such as the semantics of the parallelism construct invoked, data consumed by a task, and explicit information inserted by the toolchain, for the runtime. These affect the choice of what resources to assign to a given task, and when to suspend and resume tasks. + +Portability improves because only the \emph{interface} to constructs is encoded in the executable. Implementation is free to change from one processor to another, or even from one level of a machine's hierarchy to another. + +\subsection{Communications via firm-ware} + +Another portability benefit is realized when firm-ware becomes the application gateway to communication. This lets parallelism constructs be application-oriented, merely implying communications, without specifying or controlling details. + +Instead, the firm-ware controls activities such as marshalling data and invoking the hardware to communicate it, while linking the communication status to creation, suspension, and resumption of tasks. + +Figure X illustrates the breakdown of responsibilities, and Figure X shows dynamically the steps of invoking the firmware, sending communications, and suspending and resuming virtual processors that animate the tasks. + + + +\subsection{Communication via separate helper processors} + +Placing communication inside the firm-ware makes it practical to add separate helper processors that overlap communication with computation, as illustrated in Fig \ref{figCommProcr}. These processors execute separate firm-ware, supplied either by the OS, or as part of the executable. + + + +\begin{figure}[ht] + \center{ + \includegraphics[width=3in, height=1.5in]{../figures/Separate_comm_processors.eps} + } + \caption + {Communication is performed between local memory and remote memories via a separate communication processor. This processor executes firm-ware that is loaded under OS control. For example, it may run a standard software-cache or run scatter-gather code extracted from the application. + } +\label{figCommProcr} +\end{figure} + + + +A cogent example is an application with complex data structures that are communicated between long-running tasks. During a task, some portion of the data-structure is bundled up and sent to another task. + +The language provides constructs for rendez-vous style send and receive, and constructs that identify the bundle-data and unbundle-data code. Send and receive are implemented as part of the language, as runtime firm-ware. In contrast, the bundle and unbundle code is extracted from the application by the toolchain and packaged into the executable. During the run, an OS call causes that bundle and unbundle \emph{communication} firm-ware to be linked into the communication processors. + +When a task executes send or receive, the firm-ware swaps the context out, suspending the task, and replaces it with a non-blocked task. Simultaneously, the firm-ware causes the communication processor to execute bundle or unbundle code. When communication completes, the task is unblocked. + + + + This tight integration of communication with scheduling of tasks is an example of application information driving scheduling. It allows the firm-ware to decide which core to assign a task to based on application code, while maintaining ultra-low overhead. + + + +Such bundle/unbundle doesn't work as well in cases where the data consumed has little predictability, or the application doesn't provide gather-scatter or bundle-unbundle information. In this case, the OS can link standard software-cache firm-ware into the communication processors. + +Such a cache has the advantage of being able to swap-out tasks when it misses. If the hardware makes the cost of switching tasks be on the order of a normal function call, this scheme provides an efficient way to overlap cache misses with useful work, without the large area and energy overhead of out-of-order pipelines.. + + Another potential advantage is adjusting the cache characteristics during the run to better match the application. The characteristics of the phase of computation can be measured, or the toolchain can insert the results of analysis. + +This would ideally be coupled with scratch-pad memory that is augmented with hardware that can treat a section of the memory as tags. Special op-codes are implemented in the communication-processor to configure the tag memory, and then to cause tag-comparisons, and so on. Previous work suggests that such a software cache would be only slightly slower than normal hard-wired caches, with modest area and energy overhead []. + +\subsection{Speculation and Fast Control Message Support} + +Hardware support for speculation will work especially well with a firm-ware runtime. Transactional memory[], thread-level speculation[], and higher-level speculative constructs[] could be all supported by generic lower-level mechanisms, which are in turn invoked by the firm-ware runtime. + +This arrangement has the benefit of isolating hardware from a language's consistency-model and execution-model. There is no longer a large penalty for mis-match. To get this decoupling, hardware is simplified, by factoring the semantics out, leaving only generic ``ordering'' primitives. + + + +\begin{figure}[ht!] + \center + { \includegraphics[width=3in, height=1.5in]{../figures/Speculation_HW_support.eps} + } + \caption + { + } +\label{figSpecHW} +\end{figure} + + + +Fig \ref{figSpecHW} Illustrates such a refactoring, with hardware support for consistency and speculation. Example primitives include check-pointing, sand-boxing, and tie-points [cite web with tie-point videos], none of which imply application-visible semantics. Rather, they are used inside the firm-ware runtime to build transactional memory, thread-level speculation, and consistency models such as acquire-release, or flush-on-command. + +For check-pointing, local memory has tags, just as in caches, but with an additional field that holds a check-point number. Writes are only performed to lines with the same check-point number, and if none exist, a read is performed, of either the most recent previous check-point or fresh from remote memory. The hardware supports sending and comparing lists of lines with the same check-point number, as well as sending the lines from a particular checkpoint. This efficiently supports Thread-Level Speculation, with simple roll-back and commit. + +Sandboxes use the same hardware, except instead of storing the check-point number, the extra tag holds the sandbox ID. For transactional memory, each transaction started gets its own sandbox ID. This supports the TCC style transactional memory implementation[cite Lujan]. + +Checkpoints may also be used to support shared-memory style consistency models, but speculatively. New check-points are periodically generated, while previous ones are examined for conflicts. Examination takes place in communication processors, supported by hardware for comparing lists of tags. Conflicts cause roll-back, and restart with updated state from one of the conflicting local memories. + + Such hardware can also be used to turn off the tight consistency of current snooping-based protocols for the bulk of computation, saving time and energy in the code that doesn't need it. Such consistency is only enabled for the few specialized portions of code that implement synchronization and communication using shared-variables, essentially for passing control-messages, such as in software-based mutex algorithms. + +Another alternative is to only update shared memory when synchronization constructs indicate handoff of ownership. This uses the sandbox hardware to track individual objects or data structures. The synchronization construct in the runtime firm-ware triggers the communication firm-ware to update all objects on the core gaining ownership, from modifications made on the core giving up ownership. This not only eliminates the time and energy lost to snooping and directory protocols, but also simplifies the programming model and removes non-portable shared-memory code from executables. + +These approaches rely upon having fast control messages that communicate lists of tags between cores, and allow the firm-ware runtimes to use only local data. +Runtime performance is highest when each core has its own local runtime state. Specialized high-speed ``control'' messages in hardware also let the local runtimes communicate constraint updates, and explicitly send task-stubs, for load-balance, to each other. + +Such internal-to-runtime messages have only small amounts of data, while their latency is crucial to the runtime's responsiveness. A slowly responding runtime will leave its core idle more often, because the rate of handling internal bookkeeping about tasks is slower than the rate of finishing those tasks. It is in this case that fast control messages become crucial [Charm++ runtime paper]. + +\subsection{Example} + +To illustrate such hardware in action, we walk through an application binary invoking the ``acquire mutex'' parallelism construct: +\paragraph{setup and switch} +At the appropriate place in the binary, instructions load one register with the pointer to a mutex structure, and another register with the pointer to the virtual-processor (VP) requesting the mutex-lock. Next, the \texttt{switch} instruction executes, which switches fetch over to the firm-ware of the runtime, while saving the stack and frame pointers into the data-struct of the requesting VP. + +In this example, the hardware specifies a ``virtual processor'' (VP) data structure. It begins with a hardware defined portion that the \texttt{switch} instr automatically manages. + +\paragraph{runtime internals} +After \texttt{switch}, runtime code executes from the protected firm-ware. The code for mutex-acquire expects a pointer to a mutex struct to be in a particular register, checks the ``current owner'' field, and if empty writes the pointer to the VP (held in another register) into it. It then marks the VP as unblocked. Similarly, if the mutex is already owned, it places the VP into the mutex struct's queue, where it remains blocked. + +Most importantly, if the mutex is already owned, the runtime swaps the requesting VP out from the hardware context. It swaps in an unblocked VP. + +The execution time of this can be on the order of 10 cycles. Such speed requires hardware support for swapping VPs in and out, such as set-aside cache or scratch-pad memory with a wide port to registers, and speculative access to the mutex data-structure. This makes all memory access local and fast. + +The speculative access would be verified while computation continues. If memory consistency is performed only upon command of the runtime, and hardware supports check-point and rollback, such as in Lujan's work[] then computation can continue without speed penalty. + +Notice that no atomic memory instructions have been used. Further, the executable contains nothing but interfaces to high-level constructs. All operations have been local and fast, despite maintaining global consistency of global address space. + + + +\section{Which should be the responsibility / functionality of the programmer, the runtime software, and the hardware?} + + +With such a hardware arrangement, the responsibilities naturally break down along the lines of a software stack. The goal of it is to support specialization, which is the process of transforming the original source into a form that is highly efficient on the target hardware. + +Each layer of the stack has some role in the specialization process, while the application, on top, provides the information that the rest of the stack needs while performing the specialization. Ideally, the application must not expose hardware assumptions nor hinder specializations for particular targets. + +The proposed hardware naturally supports such a stack. The bottom layer is the set of firm-ware runtime implementations. + +The application only exposes the interface to such runtimes. This alone doesn't ensure portability, but it goes a long way towards that goal, by removing the largest source of hardware-specific information. + + +Such a stack supports high productivity through domain-specific languages, making them simple to create, easy to port across hardware, and high performance. The application programmer is responsible only for application-relevant concepts, reducing their learning curve and matching their mental model to the language. They have domain-specific parallelism constructs provided, either embedded-style as library calls, or with compiler support. + +The constructs help specialization by identifying the tasks, the constraints on scheduling the tasks, and the data to be communicated between tasks. + +In addition, high-quality specialization requires certain ``helpers"[]. These enable: 1) modifying the layout and order of access of data, 2) modifying the size of a task, both the data consumed and code executed by it, and 3) predicting both execution-time and data consumed by each task. + +The helpers are either derived by the toolchain, or encoded directly in the application via suitable constructs. Either way, the domain-specific constructs must be designed such that the information is captured, and convenient for the tools to extract. + + + +\section{Specific Topics of Interest} +Now that a position has been stated, let us examine how it applies to the topics of interest, to check its consistency and usefulness. +\paragraph{enabling future parallel programming models} + The concept of switch-to-runtime appears to be fully general, such that it supports all current and any foreseeable parallel programming models. It maintains very low overhead for them, by embedding the switch mechanism in the pipeline and providing hardware support for common runtime constraint-management and assignment operations. The combination of software flexibility, with efficiency, and the added bonus of bringing application information into the lowest-hardware-level resource management appears strong. + +\paragraph{innovative architectural execution models} Our position doesn't necessarily advocate a particular architectural execution model. However, the concept of switch-to-runtime cleanly separates the hardware execution model from the programming model, which is a benefit because it gives hardware more freedom to explore, without code legacy constraining it. However, high-speed internal-to-runtime messages, speculation support, and decoupled communication processors may be considered elements of an architectural execution model. + +\paragraph{novel memory hierarchies} -- helper cores run code for movement + +\paragraph{simplified and scalable memory models} -- name-space idea + +\paragraph{high-level constructs for on-chip communications} -- implemented in plugin + +\paragraph{characterization of the runtime overheads of parallel applications} + +\paragraph{future directions in programming massively parallel systems} hierarchy of runtimes, each level tuned to one level in HW hierarchy, algorithms and code that arrange data and perform computation in a ``fractal'' arrangement, with each level of hardware looking the same in terms of communication and computation activity. Thus, communication within the computation scales the same as communication available in the hardware scales, with level in the hierarchy. + +\paragraph{potential bottlenecks for future parallel systems} +communication-to-comp ratio in hardware is worsening.. must find hierarchical approximations to problems, that accumulate lower-level results, so amount of comm decreases as go up in the HW hierarchy. + + +================================== + +-] Main programmer visible elements: causal ordering, names of data (pointers inside data-structs), communication of data, operations applied to data, units of work, scheduling events, resulting concrete sequences of work-unit instances, tied together at certain points (for dataflow, is the firing of operations on data-sets, for functional is the application of lambda to data-instances -- the tie is where data instance output flows to multiple inputs) + + +-] Runtime support includes: + +-] "speculative exclusive access to local memory-line" + +-] ultra-fast control messages between cores for use *inside runtime* only + +-] Fast context switching.. either a reserved HW ctxt that is just for the runtime or else HW support for saving a ctxt check-point and later restoring it (in universal runtime, save ctxt checkpoint before using that ctxt to do runtime code) + +-] HW to create a "soft" ctxt (a virtual processor with stack), checkpoint it and restore a checkpoint.. + +-] HW to accelerate common parallelism-construct ops, like hash-table, queue, search-for-match (ex is runtime impl of mutex and cond vars via queues and dataflow via hash-table) + +-] HW for multi-context stack (stuff talked about with Albert) + +-] Malloc and Free in hardware, for Virtual Procr create, and for namespaces + +-] HW to support "namespace", which is a chunk of allocated memory that a virtual-processor sees.. all pointers within a namespace are offsets from the start of the namespace.. so have a reserved register that holds namespace base addr, and pointers are added to that to get final addr. Makes pointers equivalent to global, but relocatable. A namespace is essentially a stack with only one frame. When access an out-of-namespace pointer, the target namespace is accessed, the data brought over, added to the end (or malloc'd into the namespace), and pointers within the data are translated to new offsets. This provides automated HW management of distributed memories. If out-of-namespace pointer is within same addr-space, then it is directly accessed -- HW has a number of base-addr regs, which it can swap in and out + +-] HW for tracking changes in local memories (whether cache or scratch-pad, HW support for "this unit contains changes from previous mark-point" -- for cache, means "line is dirty", for scrath-pad, means "line has been written since previous check-point") + +-] HW support for speculation.. transactional memory is a speculation mechanism + +-] HW support for independent code that manages memory transfers, such as scatter-gather, fill namespace from remote memory (runs in separate context, moves data between local memory and remote, including main-memory -- the context has access to the "changed" markers) -- this code performs translation of pointers from previous memory-space to new memory-space.. so pointers become base plus offset where base is start of the memory-space) + +-] HW support for memory spaces.. all data is viewed as existing within a memory-space, where that memory-space is a HW entity.. it has a start address and a length, so all pointers are offsets from the start addr (goes back to early main-frame ideas) In code, no difference from shared-memory -- all data is within a data-struct or array, and data-structs contain pointers -- difference is that code is supplied either by language-impl or by programmer that translates the pointers when data is copied or moved to a different memory-space. Each memory-space exists inside an addr-space, but is fully repositionable just by changing the base pointer.. Thinking one memory-space per virtual processor (SW ctxt)? + +====================== + +Vision: app invoking a parallelism construct equals switch over to runtime HW ctxt (or checkpoint current), then perform construct semantics using the high-speed comm.. As an example, to implement the CAS instr, would switch to runtime, perform "exclusive access to memory-line" instr then compare, brch, write, etc + +=================================== +Taking a software stack as the organization of parallel software, with application code at the top, held within development tools, and resting upon a language interface.. (PStack picture) note, the runtime is separate from the executable, in this stack. The separation allows a single executable to run without modification on several versions of hardware, even though the runtime uses specialized hardware instructions. + +The end point is the triple goal: Productivity, Performant-Portability, and Adoptability. + +-] Productivity comes from a combination of language design that provides a mental model close to the applications while hiding any influence from hardware + +-] Performant-Portability is the most difficult technically, and boils down to the process of specializing code to the hardware. This process can span multiple points in an application's life-time, which correspond to multiple levels of the software stack. For example, compiler transforms, and then runtime choices (auto-tuners), and even swapping particular HW abstractions is part of specializing code to end-hardware. + + +Then, responsibilities are assigned to layers and interfaces within the software stack: + +Application Layer: + +-] state features of the application, in terms of constructs provided by language interface (constructs can be "embedded" into base sequential language or base parallel lang being enhanced -- for continuity with current code bases) + +Language Interface: + +-] Identify Units of work + +-] state constraints on scheduling those units + +-] provide what specialization needs to manipulate data layout and access order (specialization spans toolchain, runtime, and base HW abstraction) + + +-] provide for toolchain to manipulate data-size of work-unit and code-content of work-unit, provide for data ancestry ("data footprint") to be tracked among work-units, provide for prediction of execution time of a work-unit, for real-time provide stating real-time related constraints on scheduling of units (latency, deadlines, quality relationship) +-- note, these don't all have to be language constructs, but could be, for example, code-snippets supplied to the language, via a construct. The snippets are then used either in the toolchain or in the runtime. Examples: DKU for task re-sizing, WorkTable for dynamic dependencies (H264 wait-unitl example) +-- purpose of each is in terms of the specialization process. Specialization is the embodiment of performant portability -- the term means any changes to UCC done for purposes of performance (define UCC). + +Toolchain Layer: + +-] Perform first step of specializing code to hardware + +-] May include tools that bring experts on specialization into the process.. provide them with visualizations, and let them tune code choices and control transforms the tools perform + +-] Often involves inserting code that performs down-stream specialization, such as an autotuner (which makes final selection of parameters for data layout or kernel version, etc) + +Runtime Interface: + +-] Provides a standard way for executable to talk to runtime.. allows the runtime to be implemented with hardware-specific parallelism-helper instructions (as suggested in part 2) without tying the executable to particular hardware. Take three different HW platforms, impl runtime on each using instrs only that one platform has, but then single executable runs unchanged on all. + +-] Responsible for transmitting performance and specialization information from toolchain layer to runtime layer. This includes code that manipulates work-unit sizes, and data-layout and access pattern, as well as predictors of execution time of work-units and ways to identify and track data footprint of work-units. + +Runtime Layer: + +-] Contains implementations of the parallelism constructs that create units of work, and implementations that enforce constraints on assigning the work to hardware, for animation. + +-] Responsible for presenting consistent interface to toolchain layer, using specialization information to adjust work-unit sizes, using data-footprint information to choose hardware with least communication needed, using exe-time prediction to choose best ordering that overlaps the most communication and saves up "free" work to overlap bottlenecks in constraint-graph (dependency graph). + + +Abstraction Interface: + +-] Responsible for providing a uniform view of hardware to the runtime, including primitives for check-pointing context, creating new virtual processors, switching contexts, performing communication, bundle/unbundle + + +Abstraction Layer: + +-] Whatever of the above mentioned helpers are not implemented directly in HW, implement them in SW in this layer. + +-] provide services for the runtime to use -- such as communications, creation of virtual processors, memory allocation, and so on.. + +HW Interface: + +-] should provide as much of what the abstraction layer contains as is reasonable. Whether HW implements everything, and so replaces the abstraction layer, or some set of helpers that simplify and speed up the abstraction layer depends on how mature the abstraction is and area/energy/design-time/performance tradeoffs. + + +\section{Conclusion}\label{secConclusion} + + + + +\bibliography{Bib_for_papers} + +\end{document} diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/Future_Architecture/latex/Future_Architecture.tex.Backup --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Future_Architecture/latex/Future_Architecture.tex.Backup Sun Apr 08 09:00:10 2012 -0700 @@ -0,0 +1,547 @@ +% + + +\documentclass[conference]{IEEEtran} +% +%\usepackage{makeidx,geometry,amssymb,graphicx,calc,ifthen} +\usepackage{amssymb,graphicx,calc,ifthen} +% + +% *** CITATION PACKAGES *** +% +%\usepackage{cite} +% cite.sty was written by Donald Arseneau +% V1.6 and later of IEEEtran pre-defines the format of the cite.sty package +% \cite{} output to follow that of IEEE. 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Basically, +% \url{my_url_here}. + + + + + +% *** Do not adjust lengths that control margins, column widths, etc. *** +% *** Do not use packages that alter fonts (such as pslatex). *** +% There should be no need to do such things with IEEEtran.cls V1.6 and later. +% (Unless specifically asked to do so by the journal or conference you plan +% to submit to, of course. ) + + +% correct bad hyphenation here +\hyphenation{op-tical net-works semi-conduc-tor} + + +\begin{document} + +\bibliographystyle{plain} +% + +\title{Position: Provide Hardware Support for Runtimes, Rather than Specific Parallelism Constructs} + +\author +{ + \IEEEauthorblockN{Sean Halle} + \IEEEauthorblockA + { + Open Source Research Institute\\ + Email: sean.halle@osri.org + } +} + + +\maketitle +% + +\begin{abstract} +This is a position paper, whose purpose is to provide food for thought and a starting point for debate. Although, the ideas are extrapolations from published work on runtime systems and hardware abstractions that have been implemented and successfully demonstrated. + +The main premise is that no parallelism constructs should be directly implemented in hardware, but rather separated into a new category of \emph{firmware} that is tightly integrated into the processor pipeline and managed by the OS. We describe hardware structures that allow traditional thread constructs, domain-specific constructs, transactional memory, and even consistency models be implemented with extremely low overhead, as well as cooperatively engage the language's runtime into pipeline-level hardware-resource management. + +We further take the position that software should be organized, into a stack, based around \emph{specialization} of source to target hardware. Each layer of the stack has a role in the specialization process, which spans the lifetime of application code as it goes through the stages of, development, transformation to hardware-specific form, installation, and execution. Hence, the toolchain, hand-tuning, auto-tuners, multi-kernels, profiling, and binary optimization are all viewed as part of specialization. We describe infrastructure to encapsulate and organize these. +\end{abstract} + + + +\section{What parallel abstractions should the hardware provide?} + +Our position is that the hardware should not directly supply any parallel abstractions. Instead, it should supply a mechanism that elevates the language runtime to the status of a Hardware Abstraction Layer, which is separate from the executable and separate from the OS. Thus, parallel abstractions are implemented as soft-extensions to the hardware. With suitable support, many firmware-implemented parallel abstractions would require only a handful of instructions with a similarly low number of cycles of overhead. + + +\begin{figure}[ht] + \center{ + \includegraphics[width=3in, height=2in]{../figures/Substitute_instr_with_firm-ware.eps} + } + \caption + {A special op-code is recognized by the decode stage, and triggers fetch of instructions from firm-ware. The firm-ware instrs are provided to the OS as a ``hardware driver", and implement the runtime behavior of a language. The application communicates to the runtime by placing pointers to data-structures into registers just before executing the ``switch to runtime" instruction, which starts the fetch from firm-ware. Helper instructions accelerate common runtime operations, such as hash-table lookups, communication, search-for-optimum, and so on. + } +\label{figTimeMapping} +\end{figure} + + +Precedence for such soft-extensions to instruction sets exists. The Alpha chips from DEC provided firmware that implemented complex VAX instructions this way. A VAX ``firmware" instruction was executed by switching fetch over to a special memory that contained normal Alpha instructions, which implemented the functionality of the VAX instruction. + +An analogous approach is illustrated in Figure \ref{figTimeMapping}. Here, one op-code is set aside as the ``invoke runtime" operation. Its execution causes instructions to switch to fetching from the firm-ware. Information is communicated via register contents, which point to data-structures that include a hardware defined portion, and a language defined portion. + +This firmware was written by the language-provider, so it is separate from the executable. It implements the behavior of parallelism constructs of the language. + +Such an approach addresses security, portability, and efficiency. It is secure because the OS controls the firm-ware. It is portable because the executable only contains the \emph{interface} to the constructs (implementation is separate). It is efficient because the firm-ware runs in user-space, while a switch costs the same as the \texttt{call} instruction. It also improves application performance, if the hardware gives the firm-ware control over low-level behaviors, such as hardware-supported swapping of contexts and control of hybrid cache/scratchpad memory. + +An important feature, currently sought after, is that application information can directly affect hardware-level scheduling, communication, and other resource management. This is because they take place inside the runtime which receives application information each time it is invoked. Such application information includes the semantics of the parallelism construct invoked, data consumed by a task, and explicit information inserted by the toolchain, for use by the runtime. These affect the choice, of what resources to assign to a given task, and when to suspend and resume tasks. + +Portability improves because only the interface to constructs is encoded in the executable. Implementation is free to change from one processor to another, or even from one level of a machine's hierarchy to another. + +\subsection{Communications via firm-ware} + +Another portability benefit is realized when firm-ware becomes the application gateway to communication. This lets parallelism constructs be application-oriented, merely implying communications, without specifying or controlling details. + +Instead, the firm-ware controls activities such as marshalling data and invoking the hardware to communicate it, while linking the communication status to creation, suspension, and resumption of tasks. + +Figure X illustrates the breakdown of responsibilities, and Figure X shows dynamically the steps of invoking the firmware, sending communications, and suspending and resuming virtual processors that animate the tasks. + + + +\subsection{Communication via separate helper processors} + +Placing communication inside the firm-ware makes it practical to add separate helper processors that overlap communication with computation. These processors execute separate firm-ware, supplied either by the OS, or as part of the executable. + +A cogent example is an application with complex data structures that are communicated between long-running tasks. During the task, some portion of the data-structure is bundled up and sent to another task. + +The language provides rendez-vous style send and receive constructs, along with constructs that identify the bundle-data and unbundle-data code. The send and receive are implemented as firm-ware, and supplied as language ``drivers" that the OS loads. In contrast, the bundle and unbundle code is processed by the toolchain and translated into firm-ware that is packaged into the executable. During the run, the bundle and unbundle firm-ware is linked into the communication processors via an OS call. + +When a task executes send or receive, the firm-ware swaps the context out, suspending the task, and replaces it with a non-blocked task. Simultaneously, the firm-ware causes the communication processor to execute bundle or unbundle code. When communication completes, the task is unblocked. + + + + This tight integration of communication with scheduling of tasks is an example of application information driving scheduling. It allows the firm-ware to decide which core to assign a task to based on application code, while maintaining ultra-low overhead. + + + +Such bundle/unbundle doesn't work as well in cases where the data consumed has little predictability, or the application doesn't provide gather-scatter or bundle-unbundle information. In this case, the OS can link standard software-cache firm-ware into the communication processors. + +Such a cache has the advantage of being able to swap-out tasks when it misses. If the hardware makes the cost of switching tasks be on the order of a normal function call, this scheme provides an efficient way to overlap cache misses with useful work, without the large area and energy overhead of out-of-order pipelines.. + + Another potential advantage is adjusting the cache characteristics during the run to better match the application. The characteristics of the phase of computation can be gathered, or the toolchain insert the results of analysis. + +This would ideally be coupled with scratch-pad memory that is augmented with hardware that can treat a section of the memory as tags. Special op-codes are implemented in the communication-processor to configure the tag memory, and then to cause tag-comparisons, and so on. Previous work suggests that such a software cache would be only slightly slower than normal hard-wired caches, with modest area and energy overhead []. + +\subsection{Speculation and Fast Control Message Support} + +Hardware support for speculation will work especially well with a firm-ware runtime. Transactional memory[], thread-level speculation[], and higher-level speculative constructs[] could be all supported by generic lower-level mechanisms, which are in turn invoked by the firm-ware runtime. + +This arrangement has the benefit of isolating hardware from language's consistency-model and execution-model. There is no longer a penalty for mis-match. To get this decoupling, hardware is simplified, by factoring the semantics out, leaving only generic ``ordering'' primitives. + +Example primitives include check-pointing, sand-boxing, and tie-points [cite web with tie-point videos], none of which imply application-visible semantics. Rather, they are used inside the firm-ware runtime to build transactional memory, thread-level speculation, and consistency models such as acquire-release, or flush-on-command. + + In this way, the tight consistency of current snooping-based protocols can be turned off for the bulk of computation, saving time and energy in the code that doesn't need it. Such consistency is only enabled for the few specialized portions of code that implement synchronization and communication using shared-variables, essentially for passing control-messages, such as in Lamport's bakery algorithm. + +An alternative to snooping based consistency is to implement all communications and constructs that rely on consistency inside the firm-ware. This not only simplifies hardware, but also removes non-portable code from executables. + +Runtime performance improves when each core has its own local runtime state. This works best with the addition of specialized high-speed ``control'' messages to the hardware. The local runtimes communicate constraint updates, and explicitly send task-stubs, among themselves. + +Such internal-to-runtime messages have only small amounts of data, while their latency is crucial to the runtime's responsiveness. A slowly responding runtime will leave its core idle more often, because the rate of handling internal bookkeeping about tasks is slower than the rate of finishing those tasks. It is in this case that fast control messages become crucial [Charm++ runtime paper]. + +\subsection{Example} + +To illustrate such hardware in action, we walk through an application binary invoking the ``acquire mutex'' parallelism construct: +\paragraph{setup and switch} +At the appropriate place in the binary, instructions load one register with the pointer to a mutex structure, and another register with the pointer to the virtual-processor (VP) requesting the mutex-lock. Next, the \texttt{switch} instruction executes, which switches fetch over to the firm-ware of the runtime, while saving the stack and frame pointers into the data-struct of the requesting VP. + +In this example, the hardware specifies a ``virtual processor'' (VP) data structure. It begins with a hardware defined portion that the \texttt{switch} instr automatically manages. + +\paragraph{runtime internals} +Runtime code now executes from the protected firm-ware location. The code for mutex-acquire expects a pointer to a mutex struct in a particular register, checks the ``current owner'' field, if empty writes the pointer to the VP (held in another register) into it, and marks the VP as unblocked. Similarly, if the mutex is already owned, it places the VP into the mutex struct's queue. + +Most importantly, if the mutex is already owned, the runtime swaps the requesting VP out from the hardware context. It swaps in an unblocked VP. + +The execution time can be on the order of 10 cycles. Such speed requires hardware support for swapping VPs in and out, such as set-aside cache or scratch-pad memory with a wide port to registers, and speculative access to the mutex data-structure. This makes all memory operations local and fast. + +The speculative access would be verified while computation continues. If memory consistency is performed only upon command of the runtime, and hardware supports check-points and rollback, such as in Lujan's work[] then computation can continue without speed penalty. + +Notice that no atomic memory instructions have been used. Further, the executable contains nothing but interfaces to high-level constructs. All operations have been local and fast, despite maintaining global consistency of global address space. + + + +\section{Which should be the responsibility / functionality of the programmer, the runtime software, and the hardware?} + + +With such a hardware arrangement, the responsibilities naturally break down along the lines of a software stack. The goal of it is to support specialization, which is the process of transforming the original source into a form that is highly efficient on the target hardware. + +Each layer of the stack has some role in the specialization process, while the application, on top, provides the information that the rest of the stack needs while performing the specialization. Ideally, the application must not expose hardware assumptions nor hinder specializations for particular targets. + +The proposed hardware naturally supports such a stack. The bottom layer is the set of firm-ware runtime implementations. + +The application only exposes the interface to such runtimes. This alone doesn't ensure portability, but it goes a long way towards that goal, by removing the largest source of hardware-specific information. + + +Such a stack supports high productivity through domain-specific languages, making them simple to create, easy to port across hardware, and high performance. The application programmer is responsible only for application-relevant concepts, reducing their learning curve and matching their mental model to the language. They have domain-specific parallelism constructs provided, either embedded-style as library calls, or with compiler support. + +The constructs help specialization by identifying the tasks, the constraints on scheduling the tasks, and the data to be communicated between tasks. + +In addition, high-quality specialization requires certain ``helpers"[]. These enable: 1) modifying the layout and order of access of data, 2) modifying the size of a task, both the data consumed and code executed by it, and 3) predicting both execution-time and data consumed by each task. + +The helpers are either derived by the toolchain, or encoded directly in the application via suitable constructs. Either way, the domain-specific constructs must be designed such that the information is captured, and convenient for the tools to extract. + + + +\section{Specific Topics of Interest} +Now that a position has been stated, let us examine how it applies to the topics of interest, to check its consistency and usefulness. +\paragraph{enabling future parallel programming models} + The concept of switch-to-runtime appears to be fully general, such that it supports all current and any foreseeable parallel programming models. It maintains very low overhead for them, by embedding the switch mechanism in the pipeline and providing hardware support for common runtime constraint-management and assignment operations. The combination of software flexibility, with efficiency, and the added bonus of bringing application information into the lowest-hardware-level resource management appears strong. + +\paragraph{innovative architectural execution models} Our position doesn't necessarily advocate a particular architectural execution model. However, the concept of switch-to-runtime cleanly separates the hardware execution model from the programming model, which is a benefit because it gives hardware more freedom to explore, without code legacy constraining it. However, high-speed internal-to-runtime messages, speculation support, and decoupled communication processors may be considered elements of an architectural execution model. + +\paragraph{novel memory hierarchies} -- helper cores run code for movement + +\paragraph{simplified and scalable memory models} -- name-space idea + +\paragraph{high-level constructs for on-chip communications} -- implemented in plugin + +\paragraph{characterization of the runtime overheads of parallel applications} + +\paragraph{future directions in programming massively parallel systems} hierarchy of runtimes, each level tuned to one level in HW hierarchy, algorithms and code that arrange data and perform computation in a ``fractal'' arrangement, with each level of hardware looking the same in terms of communication and computation activity. Thus, communication within the computation scales the same as communication available in the hardware scales, with level in the hierarchy. + +\paragraph{potential bottlenecks for future parallel systems} +communication-to-comp ratio in hardware is worsening.. must find hierarchical approximations to problems, that accumulate lower-level results, so amount of comm decreases as go up in the HW hierarchy. + + +================================== + +-] Main programmer visible elements: causal ordering, names of data (pointers inside data-structs), communication of data, operations applied to data, units of work, scheduling events, resulting concrete sequences of work-unit instances, tied together at certain points (for dataflow, is the firing of operations on data-sets, for functional is the application of lambda to data-instances -- the tie is where data instance output flows to multiple inputs) + + +-] Runtime support includes: + +-] "speculative exclusive access to local memory-line" + +-] ultra-fast control messages between cores for use *inside runtime* only + +-] Fast context switching.. either a reserved HW ctxt that is just for the runtime or else HW support for saving a ctxt check-point and later restoring it (in universal runtime, save ctxt checkpoint before using that ctxt to do runtime code) + +-] HW to create a "soft" ctxt (a virtual processor with stack), checkpoint it and restore a checkpoint.. + +-] HW to accelerate common parallelism-construct ops, like hash-table, queue, search-for-match (ex is runtime impl of mutex and cond vars via queues and dataflow via hash-table) + +-] HW for multi-context stack (stuff talked about with Albert) + +-] Malloc and Free in hardware, for Virtual Procr create, and for namespaces + +-] HW to support "namespace", which is a chunk of allocated memory that a virtual-processor sees.. all pointers within a namespace are offsets from the start of the namespace.. so have a reserved register that holds namespace base addr, and pointers are added to that to get final addr. Makes pointers equivalent to global, but relocatable. A namespace is essentially a stack with only one frame. When access an out-of-namespace pointer, the target namespace is accessed, the data brought over, added to the end (or malloc'd into the namespace), and pointers within the data are translated to new offsets. This provides automated HW management of distributed memories. If out-of-namespace pointer is within same addr-space, then it is directly accessed -- HW has a number of base-addr regs, which it can swap in and out + +-] HW for tracking changes in local memories (whether cache or scratch-pad, HW support for "this unit contains changes from previous mark-point" -- for cache, means "line is dirty", for scrath-pad, means "line has been written since previous check-point") + +-] HW support for speculation.. transactional memory is a speculation mechanism + +-] HW support for independent code that manages memory transfers, such as scatter-gather, fill namespace from remote memory (runs in separate context, moves data between local memory and remote, including main-memory -- the context has access to the "changed" markers) -- this code performs translation of pointers from previous memory-space to new memory-space.. so pointers become base plus offset where base is start of the memory-space) + +-] HW support for memory spaces.. all data is viewed as existing within a memory-space, where that memory-space is a HW entity.. it has a start address and a length, so all pointers are offsets from the start addr (goes back to early main-frame ideas) In code, no difference from shared-memory -- all data is within a data-struct or array, and data-structs contain pointers -- difference is that code is supplied either by language-impl or by programmer that translates the pointers when data is copied or moved to a different memory-space. Each memory-space exists inside an addr-space, but is fully repositionable just by changing the base pointer.. Thinking one memory-space per virtual processor (SW ctxt)? + +====================== + +Vision: app invoking a parallelism construct equals switch over to runtime HW ctxt (or checkpoint current), then perform construct semantics using the high-speed comm.. As an example, to implement the CAS instr, would switch to runtime, perform "exclusive access to memory-line" instr then compare, brch, write, etc + +=================================== +Taking a software stack as the organization of parallel software, with application code at the top, held within development tools, and resting upon a language interface.. (PStack picture) note, the runtime is separate from the executable, in this stack. The separation allows a single executable to run without modification on several versions of hardware, even though the runtime uses specialized hardware instructions. + +The end point is the triple goal: Productivity, Performant-Portability, and Adoptability. + +-] Productivity comes from a combination of language design that provides a mental model close to the applications while hiding any influence from hardware + +-] Performant-Portability is the most difficult technically, and boils down to the process of specializing code to the hardware. This process can span multiple points in an application's life-time, which correspond to multiple levels of the software stack. For example, compiler transforms, and then runtime choices (auto-tuners), and even swapping particular HW abstractions is part of specializing code to end-hardware. + + +Then, responsibilities are assigned to layers and interfaces within the software stack: + +Application Layer: + +-] state features of the application, in terms of constructs provided by language interface (constructs can be "embedded" into base sequential language or base parallel lang being enhanced -- for continuity with current code bases) + +Language Interface: + +-] Identify Units of work + +-] state constraints on scheduling those units + +-] provide what specialization needs to manipulate data layout and access order (specialization spans toolchain, runtime, and base HW abstraction) + + +-] provide for toolchain to manipulate data-size of work-unit and code-content of work-unit, provide for data ancestry ("data footprint") to be tracked among work-units, provide for prediction of execution time of a work-unit, for real-time provide stating real-time related constraints on scheduling of units (latency, deadlines, quality relationship) +-- note, these don't all have to be language constructs, but could be, for example, code-snippets supplied to the language, via a construct. The snippets are then used either in the toolchain or in the runtime. Examples: DKU for task re-sizing, WorkTable for dynamic dependencies (H264 wait-unitl example) +-- purpose of each is in terms of the specialization process. Specialization is the embodiment of performant portability -- the term means any changes to UCC done for purposes of performance (define UCC). + +Toolchain Layer: + +-] Perform first step of specializing code to hardware + +-] May include tools that bring experts on specialization into the process.. provide them with visualizations, and let them tune code choices and control transforms the tools perform + +-] Often involves inserting code that performs down-stream specialization, such as an autotuner (which makes final selection of parameters for data layout or kernel version, etc) + +Runtime Interface: + +-] Provides a standard way for executable to talk to runtime.. allows the runtime to be implemented with hardware-specific parallelism-helper instructions (as suggested in part 2) without tying the executable to particular hardware. Take three different HW platforms, impl runtime on each using instrs only that one platform has, but then single executable runs unchanged on all. + +-] Responsible for transmitting performance and specialization information from toolchain layer to runtime layer. This includes code that manipulates work-unit sizes, and data-layout and access pattern, as well as predictors of execution time of work-units and ways to identify and track data footprint of work-units. + +Runtime Layer: + +-] Contains implementations of the parallelism constructs that create units of work, and implementations that enforce constraints on assigning the work to hardware, for animation. + +-] Responsible for presenting consistent interface to toolchain layer, using specialization information to adjust work-unit sizes, using data-footprint information to choose hardware with least communication needed, using exe-time prediction to choose best ordering that overlaps the most communication and saves up "free" work to overlap bottlenecks in constraint-graph (dependency graph). + + +Abstraction Interface: + +-] Responsible for providing a uniform view of hardware to the runtime, including primitives for check-pointing context, creating new virtual processors, switching contexts, performing communication, bundle/unbundle + + +Abstraction Layer: + +-] Whatever of the above mentioned helpers are not implemented directly in HW, implement them in SW in this layer. + +-] provide services for the runtime to use -- such as communications, creation of virtual processors, memory allocation, and so on.. + +HW Interface: + +-] should provide as much of what the abstraction layer contains as is reasonable. Whether HW implements everything, and so replaces the abstraction layer, or some set of helpers that simplify and speed up the abstraction layer depends on how mature the abstraction is and area/energy/design-time/performance tradeoffs. + + +\section{Conclusion}\label{secConclusion} + + + +============================= +Process technology is rapidly approaching multiple fundamental physical limits that combine to increase the cost of producing chips faster than the increase in density. Whether or not process technology continues to shrink, the economics will slow the demand for chips from future processes. This will, for the first time, shift the design decisions from being shortest time-to-market towards being the greatest efficiency per transistor -- either in computation delivered towards the goal end-user measurement such as throughput, or in energy per operation. + +The implication for processor architecture is to accelerate the trend away from "easy to program" structures such as out-of-order pipelines and coherent shared memory, and towards hierarchical designs that force application information to be exploited in explicitly managing the placement and movement of data, in order to keep it as local for as much of the computation as possible. The cost of communication will be the dominant factor driving the shape of future architectures, both from a computation-bottleneck cost and an energy per operation cost. + +Integration will be pushed towards the third dimension in order to mitigate the communication costs -- indeed main memories have long been on that path. This approach will hasten the development of 3 dimensional integration processes. The architecture implication is that + + +========== + +\bibliography{Bib_for_papers} + +\end{document} diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/Holistic_Model/Perf_Tune/latex/Holistic_Perf_Tuning.tex --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/Holistic_Model/Perf_Tune/latex/Holistic_Perf_Tuning.tex Sun Apr 08 09:00:10 2012 -0700 @@ -0,0 +1,262 @@ +%&latex +%%---------------------------------------------------------------------- +%% ieeepes_skel.tex +%% +%% Skeleton file for papers for the IEEE Power Engineering Society using +%% package ieeepes. +%% +%% Not copyrighted. Copy this file to a different name and fill in your +%% text. +%% +%% Volker Kuhlmann +%% c/o EEE Dept +%% University of Canterbury +%% Private Bag 4800 +%% Christchurch, New Zealand +%% Email: KUHLMAV@ELEC.CANTERBURY.AC.NZ +%% +% 1.3 13Apr99 Updated for ieeepes 4.0. +% 1.2 16Nov95 Fixed discussion, closure. Added summary. +% 1.1 12Nov95 Finished first release. +% 1.02 09Nov95 Option PStimes. +% 1.0 07Nov95 Created. +%%---------------------------------------------------------------------- + +\documentclass[draft]{article} + + +\usepackage[% + % psphotos,% % uncomment those options you want + % photofit,% + % draft,% + % PStimes,% + ]{ieeepes} + + + +\title{Multi-core Performance Tuning Using Semantic Information Collected by Instrumenting the Language Runtime} + +\author{ + Nina Englehardt\\ + TU Berlin +\and + Sean Halle\\ + TU Berlin +\and + Ben Juurlink\\ + TU Berlin +} + + + +\begin{document} + + +% This \maketitle command is required from ieeepes version 4.0, to make +% ieeepes work correctly with newer LaTeX versions. +\maketitle + + +\begin{abstract} +Put the text of your abstract here. +\end{abstract} + + + +\section{Section} + +The units are semantic information, the constraints on them are semantic information, the type of constraint is semantic information. The code executed inside a unit is semantic information. + +UCC shows application-defined constraints on units -- these are the degrees of freedom for picking assignment of work to HW resources. + +When tuning performance, these types of semantic information work together -- they make it easy to spot performance issues (idle time or runtime overhead), and then link information about the code to the issue. A visualization shows the scheduled units of work, the hardware those units are assigned to, the runtime overhead counted towards each unit, and the constraints that bounded the choice of which hardware and which order to assign the units. Further, the constraints are color-coded by language-defined type of constraint. Hence, a performance issue appears as a pattern of either idle time or overhead, and the visualization links the units involved, as seen in the visualization, directly to the code-snippet of the unit, and the parallelism-construct that the unit. + +In this paper, we present an approach for collecting this information by instrumenting the runtime of a language that is based on VMS. The instrumentation is done once for the language, then reused across applications. Despite being independent of application, it ties specific features in the visualization to specific segments of code, to make it easy to spot performance problems, simple to understand what in the code is causing the problem, and straight-forward to devise a fix for the problem. + +The visualization identifies each unit of work that is scheduled by the runtime, and indicates how much overhead was spent in the runtime to handle the constraints and choose an assignment. + +Rather than indicate how much time a communication takes, the visualization instead indicates how much idle time is caused on a core as a consequence of that communication. This is the most useful-to-observe cost, of the communication. It naturally accounts for overlap, and only alerts the person tuning when there is a true cost, when the core idles. + +The second aspect of communication is the emergent effect of cache misses on computation rate. As such, the relative size of work-units is visualized, which includes the cost of cache misses, given a shared-memory multi-core machine. + +Hence, the three prevalent classes of performance loss are clearly displayed by our visualization: runtime overhead (including lock acquisition time), + + + +Properties of VMS make it easy to instrument other languages, so the technique is straight-forward to apply to any VMS-based language. For UCC, have to make own data struct for lang-specific dependencies. For units, can be generic and pulled down into VMS. VMS provides support for the instrumentation -- describe standard things support. + +Copy-pastable code: identifying units, common communication constructs + +Non-copyable: weird comm-construct (N to N), have to save dependencies correspond to that. + +Key places in plugin code for instrumentation -- places in the request handler that change state of a VP -- track down in plugin code every place that VP state changes, and put instrumentation there. + +If have a mutex -- is an acquire and a release -- VP only interacts with sem env, not another VP, but dependencies are between VPs, so have to record the sequence of interactions with semantic environment to establish causality chain (even though it's a runtime causilty chain, not necessarily an app constraint) +For Vthread, no UCC, only consequence graph. + + +\subsection{Subsection} + +Text for the first sub-section. + + +\subsection{Subsection} + +Text for the second sub-section. + +\subsubsection{Subsubsection} +Text for the first sub-sub-section. + +\subsubsection{Subsubsection} +Text for the second sub-sub-section. + + +\subsection{Subsection} + +Text for the third sub-section. + + + +\section{Section} + +Text for the second section. + + + +\section{Figures and Tables} + +Text for the third section. This section has figures and tables in it. + +\begin{figure} +\centering +\fbox{figure matter} +\caption{This is the caption for figure \#1. Make sure it goes + \emph{after} the figure!} +\label{figure1} +\end{figure} + +And more text in this section. + +\begin{table} +\caption{This is the caption for table \#1. Make sure it goes +\emph{before} the table!} +\label{table1} +\centering +table matter +\end{table} + +Figure and table references: \figref{figure1}, \tabref{table1}. Use +these at the beginning and within a sentence. + +Much better is to use the Figure and Table environments, which will +take care of placing the caption correctly for you. See +\fref{figurelabel} and \tref{tablelabel}. + +Using the Figure environment: +\begin{Figure}[h]{figurelabel}% <- don't forget this percent! + {Caption for figure, Figure environment.} +\fbox{The figure matter goes here.} +\end{Figure} + +text + +Using the Table environment: +\begin{Table}{tablelabel}% <- don't forget this percent! + {Caption for table, Table environment.} +\fbox{The table matter goes here.} +\end{Table} + +And more text in this section. +And more text in this section. +And more text in this section. +And more text in this section. +And more text in this section. + + + +\section{Equations} + +Referencing equations: \equref{equation1} for whatever. +\Equref{equation1} at the beginning of a sentence. +% +\begin{equation} +equation +\label{equation1} +\end{equation} +% +text + + + +\bibliography{FilenameOfYourBibliography} + + + +\section{Test of Biographies} + +text + +\begin{biography}{Author 1}[0mm]{file.eps} +text +% there must be enough text in the first paragraph to flow around the +% photo! + +text +\end{biography} + +\begin{biography}{Author 2}[0mm]{} +text +% there must be enough text in the first paragraph to flow around the +% photo! +% Leave filename empty if photo is to be pasted in. + +text +\end{biography} + +\begin{biography}{Author 3}[0mm]{nophoto} +text +% Use filename nophoto if you don't want to put a photo there at all. + +text +\end{biography} + + +% The columns on the last page must be justified manually using +% \columnbreak. + + + +\summary + +text + + + +\begin{discussion} + {PAPER NUMBER}% + {PAPER TITLE}% + {AUTHOR NAMES}% + {DISCUSSER NAME}% + {AFFILIATION INCL ADDRESS}% + {SHORT AFFILIATION} + +text + +\end{discussion} + + + +\begin{closure}{AUTHOR NAME} + +text + +\end{closure} + + + +\end{document} + +%% +%% EOF ieeepes_skel.tex +%%---------------------------------------------------------------------- + diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/LPGPU__Arch/First_arch_paper/figures/Worker_Core.svg --- a/0__Papers/LPGPU__Arch/First_arch_paper/figures/Worker_Core.svg Sun Mar 11 09:26:44 2012 -0700 +++ b/0__Papers/LPGPU__Arch/First_arch_paper/figures/Worker_Core.svg Sun Apr 08 09:00:10 2012 -0700 @@ -14,7 +14,7 @@ id="svg2" sodipodi:version="0.32" inkscape:version="0.48.1 " - sodipodi:docname="Worker_Core.svg" + sodipodi:docname="Worker_Core_recovered.svg" inkscape:output_extension="org.inkscape.output.svg.inkscape" version="1.1"> image/svg+xml - + diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/PStack/Eco_System/Jan_2011_Hotpar_Port_Perf.pdf Binary file 0__Papers/PStack/Eco_System/Jan_2011_Hotpar_Port_Perf.pdf has changed diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/PStack/Eco_System/Jan_2011_Hotpar_Port_Perf.tm --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/PStack/Eco_System/Jan_2011_Hotpar_Port_Perf.tm Sun Apr 08 09:00:10 2012 -0700 @@ -0,0 +1,811 @@ + + + + +<\body> + ||>||>|> + + <\abstract> + Performance portability, in the sense that a single source can run with + good performance across a wide variation of parallel hardware platforms, + is strongly desired by industry and actively being researched. \ Evidence + is mounting that performance portability cannot be realized at just the + toolchain level, or just at the runtime level or just at the hardware + abstraction level. + + This is a position paper, making a suggestion for how the groups involved + can more efficiently solve the performance portability problem together. + We don't propose a soltion, at all, but rather a support system for the + players to self organize and collectively find one. \ The support system + is based on a newly discovered execution model called VMS (Virtualized + Master-Slave) [>], that fulfills the needs of an + organizing principle. The difficult work will be the on-going research + efforts on parallel language design, compilers, source-to-source + transform tools, schedulers, runtime systems, and hardware support for + parallelism. \ Although it doesn't in itself solve the problem, such an + organizing principle may be a valuable step towards a solution -- the + problem may be too complex and require cooperation of too many real-world + entities for a single-entity solution. + + We briefly review VMS, and illustrate how it could be used to give rise + to an eco-system in which performance portability is collectively + realized. \ To support the suggestion, we give measurements of the time + to implement three embedded parallel languages, and performance numbers + for them, along with measurements of the basic overhead of VMS. + + + <\with|par-columns|1> + <\with|par-columns|2> + + + Evidence is mounting that one-stop solutions to performance portability + fail to address critical real-world patterns -- for example, attempting + to place the full specialization into the toolchain + > requires a central entity that updates + all toolchains when new hardware becomes available. \ It also requires + automated re-compile for the new target and automated distribution of + multiple binaries. Otherwise, the software developers would have no way + to get their source code to run on new hardware -- their source has to + be recompiled and the resulting binary distributed. To do this for + thousands of different software development entities requires + centralization. But such a centralized approach has technical and + practical obstacles. + + Pure runtime based approaches > + imply a single binary, with the only change being the runtime system. + Without help from the toolchain to extract relevant information and + prepare it for the runtime, the amount of specialization and its + effectiveness is limited. \ In addition, the runtime has to be + separately implemented for every hardware platform, and for every + language, without much reuse. \ + + Finally, hardware abstraction based approaches, such as JIT + solutions>, place all the work of specializing + into a single place, which makes reuse difficult, forcing extensive + rewrite of JIT internals for each hardware platform, for each language. + This software cost is an issue in the embedded space where new hardware + is introduced often and has a limited market size to amortize the + software cost. \ In addition, this one-stop approach requires a + different JIT for each language, because it has to recognize + language-specific features to specialize -- or else it fails to achieve + good performance. This requires extensive work, making domain-specific + languages time-consuming and difficult to develop, and the multiple + JITs logistically awkward. + + What's needed is a system that leaves hardware free, language designers + free, and software developers free, imposing minimal restrictions on + them, while maximizing reuse of individual efforts and simplifying the + logistics. It would be merely a support system that makes the work of + each of those individual groups easier, and makes their independently + provided pieces naturally support each other. + + We take the position in this paper that such a support system has to + operate at all three levels: the language design plus toolchain level; + the runtime system level; and the hardware abstraction level. \ Sequoia + > does this in a limited way. \ We propose a more + general approach that supports languages without restricting them, has + more freedom to specialize the runtime, \ and reduces the effort to add + new target hardware. It takes advantage of VMS (Virtualized + Master-Slave) [>], which naturally provides pieces for + each level, and acts as an organizing principle. + + Section 2 gives a high-level reveiw of VMS, and Section 3 reviews + performance portability fundamentals. Section 4 then illustrates how + VMS can be used to organize an eco-system in which performance + portability is a reality. Section 5 gives supporing evidence of VMS's + suitability, with measurements of the time to implement three embedded + parallel languages, performance numbers for them, and measurements of + the basic overhead of VMS. + + + + On nomenclature, in this paper we define as a 3-tuple -- 1) + an animation event, 2) a collection of code animated, and 3) a + collection of information instances that code is animated upon. + However, we often refer to just the code plus data as a task, with the + implication that animation will take place in the future. \ This allows + us to say things like ``we create a task'', meaning we create a + combination of code plus data with the intent to animate it, and ``we + assign a task to'' which means we move the code plus data -- but at + some future time the combination shall be animated, exactly once. + + Virtualized Master Slave (VMS) is an + execution model that replaces Threads. \ In effect, it opens up the + thread-scheduler, letting the language supply its own scheduler that is + plugged-in. Along with the scheduler, the plugin also contains a + definition of concurrency constructs -- the two together complete the + runtime for a parallel language. + + The plugin is supplied separately from the application, as a dynamic + library or a device driver, which makes the runtime separately loaded + onto the hardware, turning the language runtime into a new component in + the software stack. \ The behavior of the languages's concurrency + constructs is implemented in the plugin using sequential algorithms, + reducing implementation time for the concurrency semantics to a matter + of days. \ The plugin also contains the scheduler, which gives the + language control over assigning virtual processors to physical cores. + On multi-core shared-memory machines, the run-time overhead is low, on + the order of a few hundred nano-seconds per concurrency operation. The + VMS model can be implemented as a user-space library, or existing OS + kernels can be converted to the VMS model by opening up their + scheduler, and exposing the VMS plugin interface. + + What distinguishes VMS is that it doesn't impose its own concurrency + semantics, but rather takes them as plugins. \ Hence VMS isn't a + language, but rather the creation of language runtimes. + Any language level execution model is implementable as a layer on top + of VMS, including: Actors ; Components + ; process calculi like CSP , and + Pi-calculus ; and coordination languages like Linda + . \ Likewise implementable with VMS are systems + like TBB and OpenMP, as well as hybrid languages like Sequioa, and + legacy languages that rely on Threads such as Java, and C/C++ with + pthreads. + + + + Portable performance is achieved by specializing the source code to the + hardware. \ For traditonal sequential source on sequential processors, + the specialization was the translation to machine code and optimization + that took place in the compiler. + + This one-step specialization was sufficient because most of the + performance portability was provided by using micro-architecture + hardware techniques underneath a standard instruction-set abstraction. + This has worked because, before recently, process technology has made + every generation of sequential processor faster, and parallelism could + be found at the granularity of single instructions. Also, CPU producers + have kept their instruction sets relatively fixed. + + Unfortunately, for larger-granularities of parallelism, such a + hardware-based approach to performance portability has proven + infeasible so far. \ We conjecture that the reason is, that larger + granularity parallelism is tied to the language constructs and to + application constructs (whereas instruction-level parallelism is tied + only to the machine-instruction-set constructs). Hence, information + about the language patterns and application patterns must be available + in order to exploit these larger granularities. \ The hardware cannot + make use of the larger granularities because the instruction set + abstraction provides no means to convey the necessary language and + application patterns. + + Following this intuition, we propose that to be effective, a system for + performance portability for parallel software should have a means of + identifying language and application constructs and packaging this + information in a standard format. \ Also, a hardware abstraction should + be provided that accepts such information and uses it to make + high-quality decisions about task creation, task sizing, and task + placement. + + + + VMS fits this proposal by allowing the language toolchain to extract + the application's task patterns and language patterns, and package them + in a standard format that any plugin for that language understands. As + mentioned in the review, the plugin plus VMS implementation represent + the parallel aspects of the hardware, so each language's plugin defines + the format of the task info to be handed to the hardware abstraction. + \ The first step of specializing is thus the extraction of the task + info by the toolchain. + + <\with|par-first|0fn> + |The + three places that specialization occurs. In the top box, the + toolchain extracts task information useful to the scheduler and + packages it into the binary, specializing the source to the plugin's + interface. \ In the middle, the scheduler in the plugin retrives the + info and uses it to make scheduling decisions, specializing the + binary to the hardware abstraction. At the bottom, the VMS-core + implementation hides hardware details behind the interface, + specializing the hardware to the hardware abstraction.> + + + The second step of specialization is the plugin, which uses the task + info to make high quality decisions about size and placement of tasks, + as represented in the middle of figure 2. \ The last step of + specialization is implementing the VMS abstraction on the particular + hardware. \ This combination of plugin plus VMS has the same function + that the instruction set had back in the sequential days -- it provides + a standard hardware abstraction. \ VMS has the advantage that the + abstraction is modifiable by choosing the plugin. + + <\with|par-first|0fn> + <\small-figure|> + \; + + The toolchain is split, the top portion is related to parallelism + and the bottom portion does sequential compilation of C code. In + the top box, source code is transformed into C code that has calls + inserted. They invoke the plugin, during the run, to perform + concurrency operations, such as synchronizations, sends, receives, + publish, and so on. The top box also extracts parallelism + information from the source, and encodes it as implementations of + library calls. These are later invoked by the plugin to retrieve + the information. \ In this way, the generated parallelism + information passes through any standard sequential C compiler, + which is the only hardware-specific portion. + + + + Focusing on the toolchain, we propose breaking it into two sections: + one for parallelism, the other for sequential. \ The parallelism + portion extracts the task and language information needed to make high + quality scheduling decisions. \ The sequential specializes individual + functions to the sequential cores. \ The parallelism portion remains + constant across hardware, only the sequential portion changes when the + instruction-set of the target hardware changes. + + One possible way to achieve this is to make the parallel portion + transform the original source to C code with embedded calls to the + concurrency library functions. \ During this source-to-C-plus-lib-call + transform, the information is packaged into functions in some way. + \ The resulting C-plus-lib-calls source is then compiled with the + sequential C compiler to make a binary, as depicted in Figure X. + + Meanwhile, the plugins for that language know the names of the library + functions the task information has been packaged into. \ Hence, when + the binary is linked to a plugin at load time, the task-info functions + within the binary become available to the plugin. \ They are then + called by the plugin during the run to extract the information, to make + high quality scheduling decisions. + + This scheme allows unmodified sequential compilers to be used to pass + the information along, inside of a standard binary format. \ It also + separates the parallel and sequential portions of the tool chain + cleanly, so only the relatively simple sequential C compiler changes + with hardware. \ This scheme also leaves the language designers in + charge of deciding the nature and definition of the information + carrying functions. + + These properties enable reuse of the same parallel portion of the + toolchain across chips, which is especially valuable in the embedded + market. \ With the inclusion of real-time aspects, such as latency + bounds and deadlines, this could dramatically speed up time to market + and reduce cost of introduction of new embedded chips. + + This begs the question: what kind of task information is sufficient for + parallel performance portability across the array of forseeable + parallel architectures? We propose three kinds of information: 1) + manipulators, which are able to modify the size of tasks and change the + way data is accessed, 2) information about the tasks such as type of + core they run best on, size of data footprint, predicted execution + time, and 3) real-world constraints that relate to the tasks, such as + deadlines, maximum latency for data to pass from one point in the + computation to another, and quality related information. \ Again, it is + up to the language and plugin to agree on what data is extracted, + passed, and then used for scheduling. \ Meanwhile, it is up to VMS to + provide the services and information required by the scheduler to make + use of the information. + + As research progresses, additional types of information may become + necessary, so this flexibility from the plugin system will prove key. + \ Again, the plugin plus VMS implementation are the hardware + abstraction -- the parallel equivalent of what the instruction set used + to be for sequential processors. \ The two define the behavior that the + binary expects to be present. + + This, finally, begs the question: what kind of information and services + must VMS provide to the plugin? It must expose the features of the + hardware that matter the most to performance (computation, energy, and + real-world related performance). We suggest that the memory hierarchy + and communication between the memory pools are the most important + features for parallel performance. \ However, the VMS interface should + only expose the portions of memory affectable by a runtime scheduler + (the register set usage of a sequential processor is fixed by the + binary and so not exposed). + + We suggest that most parallel architectures fall into a small number of + classes, each of which exposes sufficient structure without exposing + chip-specific details. What's important is the type(s) of cores, the + pools of memory, and the nature of communication between them. On + communication, the scheduler can treat the network statistically with + relatively simple models, independently from the topology, without + undue loss of performance >. So the main feature is + coherent memory vs distributed, which determines whether communication + can take place by shared variables in the code vs whether it needs + explicit action. + + Given this, our proposed list includes: 1) multi-core and many-core + that share a single coherent memory 2) one or more SIMD units that + share a single coherent memory 3) collections of those connected by + shared memory 4) distributed collections of those. Each memory pool, + such as a cache or scratchpad, is exposed, with the communication costs + from each pool to each other pool, and whether communication between + them is automated or explicit. Applying this to known architectures: + single-socket multi-core systems fall into 1, while adding a GPGPU puts + them also into 2 and 4. \ The Cell BE is in 1 and 4, as is the SCC. + \ Larrabee would have been in 1, 2, and 3 but may have been more + effectively treated as 1, 2, and 4. \ Traditional supercomputers made + up of shared-memory nodes connected by networks fall into 1 and 4. + + <\with|par-columns|1> + <\big-figure> + + + + + + + Figure 4 depicts how the pieces all fit together. At the top, + independent software developers write applications, in a variety of + languages. Each language defines its own format for conveying + task-related info. Independently, plugins are implemented that accept + that format, one plugin for each hardware class. This allows hardware + manufacturers to supply their own plugins, for unusual hardware + designs, and still take advantage of the existing application binaries + (non-standard instruction sets also need an install-time translator). + + The plugins, in the middle, act as a cross-bar switch, connecting the + binaries to the hardware abstractions. They are separately distributed + and loaded onto the hardware, much the way device drivers are + currently. + + At the bottom, the hardware abstraction implementations standardize the + hardware. They are mainly supplied by the hardware manufacturers, but + open-source implementations will likely also arise. + + Note that the only software developed for a new HW platform is the + VMS-core abstraction, sequential C compiler, and a bare-bones OS. + Existing applications are adpated via the plugin and abstraction. + + We expect that a small number of HW classes will quickly come to + dominate, which will encourage later HW development to fit within the + dominant classes. As a result, a standard set of sequential C compilers + will emerge, allowing software developers to perform a single + compilation pass. For fine tuning of compilation + choices, we expect install-time binary rewriters or run-time binary + optimizations. + + The end-result is that no centralized control is needed. Language + designers are free to innovate, inventing new concurrency constructs + and communication abstractions, and need as little as just the set of + plugins, or just the source-to-C translator to reach all the standard + hardware platforms. Likewise, hardware manufacturers are free to + innovate, needing minimal software development for a new chip to enjoy + access to all the applications.\ + + The set of plugins is the key to this portability, and the funnelling + of many applications to the same parallelism information at the top, + and many hardware platforms to the same abstraction at the bottom. + + + + <\with|par-columns|2> + + + <\with|par-columns|2> + + + As far as a binary is concerned, the parallel behavior of the hardware + is represented by the combination of VMS plus the plugin, while the + \ sequential behavior of the hardware's processing-elements is + represented by the Instruction Set of each core. + + The VMS implementation is made up of a master virtual-processor that + receives and calls the plugin functions, and a ``core-controller'' that + handles transferring the physical-core between animating the master + virtual processor and animating the application's virtual processors, + but according to the decisions the plugin functions make, when called + by the master VP. As part of invoking a concurrency construct, an + application VP attaches to itself a request destined for the master VP, + then suspends. We next review how this request reaches the plugin's + concurrency-construct implementation, called the requestion handler, by + walking through the steps VMS takes during operation. + + <\with|par-first|0fn> + <\with|par-left|0cm> + + + + + Internal elements of VMS + implementation > + + The steps of operation are numbered in + Figure . \ Taking them in order, 1) + scans the scheduling slots to see which ones' + slaves have suspended since the previous scan. \ 2) It hands these to + the request handler plugged-in. \ \ 3) The data in the request causes + manipulation of the data structures within the semantic state. \ These + structures hold all the slaves currently in the blocked state. \ 4) + Requests cause slaves to be moved to the ready-container, which was + implemented as an array of simple queues, one to each physical core. + Which core receives the slave is under plugin control, determined by a + combination of request contents, semantic state and physical state. 5) + During the scan, the also looks for empty slots. + It calls the scheduler plug-in function, which chooses a slave from the + ready container. \ 6) The then places the slave + VP's pointer into the scheduling slot, making it available to the + . \ 7) When done with the scan, + suspends, switching animation back to the . \ 8) + takes slave VPs out of the slots, then 9) switches + animation to them. \ 10) When a slave self-suspends, animation returns + to the , which picks another, until 11) all slots + are empty and the switches animation to the + . + + All of that happens on each core separately, but in this + particular implementation we use a central to + ensure that only one core's can be active at any + time. \ This guarantees non-overlap of trace-segments from different + s, allowing the plugins to use sequential + algorithms, without a performance penalty, as verified in Section 5. + + + Performance> + + We implemented blocked dense matrix multiply and ran on + a Core2Quad 2.4Ghz chip. + + Time to implement the runtime for the + three parallel languages averages 2 days. \ As an example of + productivity, adding nested transactions, parallel singleton, and atomic + function-execution to SSR required a single afternoon, totaling less than + 100 lines of C code. Table summarizes + implementation times. + + |||||||>||||>||||>||||>||||>>>>|Person-days + to design, code, and test the library plus plug-in of each language, in + the order attempted. L.O.C. is lines of (original) code, excluding + libraries and comments.>>>>>> + + \ seen in Table + . + + The code has not been designed for speed, but rather to be easy to + understand and modify. In particular, the schedulers are simple queues + with no optimization for performance. + + <\with|par-mode|left> + |||||||||||||||>||||>|>|||>||||>||||>||||>||||>||||>||||>||||>||||>||||>||||>||||>||||>||||>||||>||||>>>>|Cycles of overhead, per scheduled + slave, consisting of: A) VMS-only cycles spent in VMS portion of + , B) time in the to switch + between VPs, C) Language-specific cycles spent in the plugin's Request + Handler and Scheduler, and D) obtaining the Master lock. \ ``comp + only'' column is cycles with perfect memory, ``comp + mem'' is actual + cycles. ``Plugin-concur'' is only concurrency related requests, + ``plugin-all'' includes create and malloc requests. Numbers are to two + significant digits due to variability. \ Language overhead was measured + while running Matrix Multiply.>>>>>> + + + We compare our implementation of the and + constructs against the distributed version of Cilk, in + Table , which shows that the same + application code has similar performance. + + ||||||||||||||||>|||>|||>|||>|||>|||>|||>|||>|||>>>>|Head-to-head + comparison of exe time in seconds for VCilk vs Cilk 5.4 on MM. \ VCilk + does 23% worse on large matrices that run for several seconds, but 210% + better on small matrices requiring milliseconds.>>>>>> + + \; + + Versus pthreads, our VMS based implementation has more than an order of + magnitude better overhead per invocation of mutex or condition variable + functionality, as seen in Table . + + <\with|par-mode|left> + |||||||||||||||||>|||||>|||||>|||||>|||||>|||||>|||||>>>>|Rough + measurements of cycles to perform synchronization primitives. \ For + VPThread, the first column shows computation time of plugin when all + memory accesses hit in the cache. The second column is total time, + including , , and the effects + of cache and page misses. Pthread times are deduced from round-trip + experiments. The ratio calculations are pthread vs total + VPThread.>>>>>> + + + Conclusion> + + This is a position paper, merely a suggestion for a large scale + organizing principle by which real-world entities can cooperatively + achieve performance portability. The key pattern is the funnelling of + many applications to the same parallelism information at the top, the + funnelling of many hardware platforms to the same abstraction at the + bottom, and the set of plugins that connect the two ends. + + + <\bibliography|bib|Helpers/plain|Helpers/Bib_for_papers.bib> + \; + + + \; + + \; + + +<\initial> + <\collection> + + + + + + + + + + + + + + +<\references> + <\collection> + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + + + +<\auxiliary> + <\collection> + <\associate|bib> + Hewitt10 + + Actors97 + + ComponentModel00 + + hoare78 + + milner99 + + Gelernter85Linda + + <\associate|figure> + > + + <\tuple|normal> + \; + + The toolchain is split, the top portion is related to parallelism and + the bottom portion does sequential compilation of C code. In the top + box, source code is transformed into C code that has calls inserted. + They invoke the plugin, during the run, to perform concurrency + operations, such as synchronizations, sends, receives, publish, and + so on. The top box also extracts parallelism information from the + source, and encodes it as implementations of library calls. These are + later invoked by the plugin to retrieve the information. \ In this + way, the generated parallelism information passes through any + standard sequential C compiler, which is the only hardware-specific + portion. + > + + > + + Internal elements of VMS + implementation |> + + <\associate|table> + Person-days to design, code, and + test the library plus plug-in of each language, in the order attempted. + L.O.C. is lines of (original) code, excluding libraries and + comments.|> + + Cycles of overhead, per + scheduled slave, consisting of: A) VMS-only cycles spent in VMS portion + of |language||master_loop>, + B) time in the |language||core_loop> + to switch between VPs, C) Language-specific cycles spent in the + plugin's Request Handler and Scheduler, and D) obtaining the Master + lock. \ ``comp only'' column is cycles with perfect memory, ``comp + + mem'' is actual cycles. ``Plugin-concur'' is only concurrency related + requests, ``plugin-all'' includes create and malloc requests. Numbers + are to two significant digits due to variability. \ Language overhead + was measured while running Matrix Multiply.|> + + Head-to-head comparison of exe + time in seconds for VCilk vs Cilk 5.4 on MM. \ VCilk does 23% worse on + large matrices that run for several seconds, but 210% better on small + matrices requiring milliseconds.|> + + Rough measurements of cycles to + perform synchronization primitives. \ For VPThread, the first column + shows computation time of plugin when all memory accesses hit in the + cache. The second column is total time, including + |language||master_loop>, + |language||core_loop>, and + the effects of cache and page misses. Pthread times are deduced from + round-trip experiments. The ratio calculations are pthread vs total + VPThread.|> + + <\associate|toc> + |math-font-series||1Overview + and Motivation> |.>>>>|> + + + |math-font-series||2VMS> + |.>>>>|> + + + |2.1Overview of VMS + \ \ |.>>>>|> + > + + |math-font-series||3Specialization> + |.>>>>|> + + + |3.1Three-step specialization + |.>>>>|> + > + + |math-font-series||4Eco-System> + |.>>>>|> + + + |math-font-series||5> + |.>>>>|> + + + |5.1Internal Workings of VMS + |.>>>>|> + > + + |Steps of Operation: + |.>>>>|> + > + + |Enabling sequential implementation of + concurrency semantics: |.>>>>|> + > + + |math-font-series||6Performance> + |.>>>>|> + + + |Setup: |.>>>>|> + > + + |Implementation-Time: + |.>>>>|> + > + + |Execution Performance: + |.>>>>|> + > + + |Head to Head: VCilk vs Cilk 5.4 \ plus + \ VPThread vs pthread: |.>>>>|> + > + + |math-font-series||7Conclusion> + |.>>>>|> + + + |math-font-series||Bibliography> + |.>>>>|> + + + + \ No newline at end of file diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/PStack/Eco_System/Jan_2011_Hotpar_Port_Perf_2.pdf Binary file 0__Papers/PStack/Eco_System/Jan_2011_Hotpar_Port_Perf_2.pdf has changed diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/PStack/Eco_System/Jan_2011_Hotpar_Port_Perf_2.tm --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/PStack/Eco_System/Jan_2011_Hotpar_Port_Perf_2.tm Sun Apr 08 09:00:10 2012 -0700 @@ -0,0 +1,849 @@ + + + + +<\body> + ||>||>|> + + <\abstract> + Performance portability, in the sense that a single source can run with + good performance across a wide variation of parallel hardware platforms, + is strongly desired by industry and actively being researched. \ However, + evidence is mounting that performance portability cannot be realized at + just the toolchain level, or just at the runtime level or just at the + hardware abstraction level. + + This is a position paper, making a suggestion for how the groups involved + can more efficiently solve the performance portability problem together. + We don't propose a soltion, at all, but rather a support system for the + players to self organize and collectively find one. \ The support system + is based on a newly discovered execution model called VMS (Virtualized + Master-Slave) , that fulfills the needs of an organizing + principle, and helps concentrate the research effort into more focused + areas. The difficult work will be the on-going research efforts on + parallel language design, compilers, source-to-source transform tools, + binary optimization, run-time schedulers, and hardware support for + parallelism. \ Although it doesn't in itself solve the problem, such an + organizing principle may be a valuable step towards a solution -- the + problem may be too complex and require cooperation of too many real-world + entities for a single-entity solution. + + We briefly review VMS, and illustrate how it could be used to give rise + to an eco-system in which performance portability is collectively + realized. \ To support the suggestion, we give measurements of the time + to implement three embedded parallel languages, and performance numbers + for them, along with measurements of the basic overhead of VMS. + + + <\with|par-columns|1> + <\with|par-columns|2> + + + Evidence is mounting that one-stop solutions to performance portability + fail to address critical real-world patterns -- for example, attempting + to place the full specialization into the toolchain + requires automated re-compile for each new target, and automated + distribution of multiple binaries. Otherwise, the software developers + would have no way to get their source code to run on new hardware -- + the toolchain has to specialize the source and the resulting binary be + distributed. To do this for thousands of different software development + entities requires centralization. But such a centralized approach has + technical and practical obstacles. + + Pure runtime based approaches imply a single + binary, with only the runtime system changing across targets. The + effectiveness of this specialization is limited because it has no help + from the toolchain to extract relevant information and prepare it for + the runtime. \ In addition, the runtime has to be separately + implemented for every hardware platform, and for every language (in + order to take advantage of language-specific constructs during + specialization), without much reuse. \ + + Finally, hardware abstraction based approaches, such as JIT + solutions, place all the work of specializing into a + single place, which makes reuse difficult, forcing extensive rewrite of + JIT internals for each hardware platform, for each language. This + software cost is an issue in the embedded space where new hardware is + introduced often and has a limited market size to amortize the software + cost. \ In addition, this one-stop approach requires a different JIT + for each language, because it has to recognize language-specific + features to specialize -- or else it fails to achieve good performance. + This requires extensive work, making domain-specific languages + time-consuming and difficult to develop, and the multiple JITs + logistically awkward. + + What's needed is a system that leaves hardware free, language designers + free, and software developers free, imposing minimal restrictions on + them, while maximizing reuse of individual efforts and simplifying the + logistics. It would be merely a support system that makes the work of + each of those individual groups easier, and makes their independently + provided pieces naturally support each other. + + We take the position in this paper that such a support system has to + operate at all three levels: the language design plus toolchain level; + the runtime system level; and the hardware abstraction level. \ Sequoia + does this in a limited way. \ We propose a more general + approach that supports (multiple) languages without restricting them, + has more freedom to specialize the runtime, \ and reduces the effort to + add new target hardware. It takes advantage of VMS (Virtualized + Master-Slave) , which naturally provides pieces for each level, + and acts as an organizing principle. + + Section 2 reveiws VMS. Section 3 reviews performance portability + fundamentals. Section 4 illustrates using VMS to support an eco-system. + Section 5 gives supporing evidence of VMS's suitability. Section 6 + concludes. + + + + On nomenclature, in this paper we define as a 3-tuple: + \animation event, collection of code animated, collection of + information the code is animated upon\. The phrase ``we create a + task'' means we create a combination of code plus data with the intent + to animate. + + Virtualized Master Slave (VMS) is an + extensible virtualization mechanism that replaces Threads. \ The + language supplies its own scheduler, which is plugged in. Along with + the scheduler, the plugin also contains a definition of parallelism + constructs, such as publish-subscribe channel, or send-receive, or + spawn-sync -- the scheduler plus parallelism constructs together + complete the runtime for a parallel language. + + The plugin is supplied separately from the application, as + a dynamic library or device driver. This makes the runtime separately + loaded onto the hardware, turning it into a new component in the + software stack. + + The VMS model can be implemented as a user-space library, or existing + OS kernels can be converted to the VMS model by opening up their + scheduler, exposing the VMS plugin interface. The parallelism + constructs are implemented using sequential algorithms, reducing + implementation time for parallelism semantics to a matter of days. + \ The plugged-in scheduler gives the language control over assigning + work to physical cores. On multi-core shared-memory machines, the + run-time overhead is low, around a few hundred nano-seconds per + concurrency operation. + + What distinguishes VMS is that it doesn't impose its own parallelism + semantics, but rather takes them as plugins. \ Hence VMS isn't a + language, but rather the creation of language runtimes. + Any language level execution model is implementable as a layer on top + of VMS, including: Actors ; Components + ; process calculi like CSP and + Pi-calculus ; and coordination languages like Linda + . \ Likewise implementable with VMS are systems + like TBB and OpenMP, as well as hybrid languages like Sequioa, and + legacy languages that rely on Threads such as Java and C/C++ with + pthreads. + + + + Portable performance is achieved by specializing the source code to the + hardware. \ For traditonal sequential source on sequential processors, + the specialization was the translation to machine code and optimization + that took place in the compiler. + + This one-step specialization was sufficient because most of the + performance portability was provided by using micro-architecture + hardware techniques that exploited instruction-level parallelism + underneath a standard instruction-set abstraction. + + We conjecture that the reason such a hardware-based approach to + performance portability has failed for parallel hardware is that larger + granularity parallelism is tied to the language constructs and to + application constructs (whereas instruction-level parallelism is tied + only to the machine-instruction-set constructs). Hence, information + about the language patterns and application patterns must be available + in order to exploit these larger granularities. \ The hardware cannot + make use of the larger granularities because the instruction set + abstraction provides no means to convey the necessary language and + application patterns. + + Following this intuition, we propose that a system for parallel + performance portability have a means to identify language and + application constructs and packaging this information in a standard + format. \ Also, a hardware abstraction should be provided that accepts + such information and uses it to make high-quality decisions about task + creation, sizing, and placement. + + + + VMS fits this proposal by allowing the toolchain to extract the + application's task patterns and package them in a format that plugins + for the language understand. The plugin represents the parallel aspects + of the hardware, so each language's plugin defines the format of task + info to be handed to the ``hardware''. The first step of specializing + is thus the extraction of the task info by the toolchain. + + <\with|par-first|0fn> + |Specialization + occurs in three places. First, in the top box, the toolchain extracts + task information useful to the scheduler and packages it into the + binary. \ This specializes the source to the plugin's interface. + \ Second, in the middle, the scheduler in the plugin retrives the + info and uses it to make scheduling decisions. This is specializing + the binary to the hardware abstraction. Third, at the bottom, the + VMS-core implementation hides hardware details behind the interface. + This is specializing the hardware abstraction to the hardware.> + + + The second step of specialization is the plugin, which retrieves the + task info, using it to make high quality decisions about size and + placement of tasks, as represented in the middle of figure 2. \ The + last step of specialization is implementing the VMS abstraction on the + particular hardware. \ This combination of plugin plus VMS has the same + function that the instruction set had back in the sequential days -- it + provides a standard hardware abstraction. \ VMS has the advantage that + the abstraction can be chosen separately for each binary, by choosing + the plugin. + + Focusing on the + toolchain, we propose breaking it into two sections: one for + parallelism, the other for sequential. The parallelism portion extracts + the task and language information needed to make high quality + scheduling decisions. \ The sequential specializes individual functions + to the sequential cores. \ The parallelism portion remains constant + across hardware, only the sequential portion changes when the + instruction-set of the target hardware changes (in effect, this moves a + portion of the compiler into an install-time, or load-time, or run-time + component that completes binary specialization). + + <\with|par-first|0fn> + <\small-figure|> + \; + + The toolchain is split, the top portion is related to parallelism + and the bottom portion does sequential compilation of C code. In + the top box, source code is transformed into C code that has calls + inserted. They invoke the plugin, during the run, to perform + parallelism operations, such as synchronizations, sends, receives, + publish, and so on. The top box also extracts parallelism + information from the source, and encodes it as implementations of + library calls. These are later invoked by the plugin to retrieve + the information. \ In this way, the generated parallelism + information passes through any standard sequential C compiler, + which is the only hardware-specific portion. + + + + One possible way to achieve this is to make the parallel portion + transform the original source to C code, with embedded calls to the + parallelism constructs. Also during this source-to-C-plus-lib-call + transform, the task information is packaged into functions in some way. + \ The resulting C-plus-lib-calls source is then compiled with the + sequential C compiler to make a binary, as depicted in Figure 2. + + Meanwhile, the plugins for that language know the names of the library + functions the task information has been packaged into. \ Hence, when + the binary is linked to a plugin at load time, the task-info functions + within the binary become available to the plugin. \ They are called + during the run to extract the information. + + This scheme allows unmodified sequential compilers to be used to pass + the information along, inside of a standard binary format. \ It also + separates the parallel and sequential portions of the tool chain + cleanly, so only the relatively simple sequential C compiler changes + with hardware. \ This scheme also leaves the language designers in + charge of deciding the nature and definition of the information + carrying functions. + + These properties enable reuse of the same parallel portion of the + toolchain across chips, which is especially valuable in the embedded + market. \ With the inclusion of real-time aspects, such as latency + bounds and deadlines, this could dramatically speed up time to market + and reduce cost of introduction of new embedded chips. + + This part of the proposal may run into + difficulties in practice. The details of architectures like vector + units and GPUs are too fine-grain for typical run-time scheduling, and + may require multi-versioned binaries or load-time or install-time + binary optimizers to fit this paper's proposal. It will require + extensive toolchain research by many groups to either realize this or + give reasonable evidence that it's not practical. + + This begs the question: + what kind of task information is sufficient for parallel performance + portability across the array of forseeable parallel architectures? + Fortunately, the support system doesn't define this, but leaves it free + to evolve as research progresses, providing an upgrade path. + + We propose three kinds of information will be sufficient: 1) + manipulators, which are able to modify the size of tasks, choose among + alternative binary versions, and change the data layout and access + pattern (such as auto-tuners injected into the binary), 2) information + about the tasks such as type of core they run best on, size of data + footprint, and predicted execution time, and 3) real-world constraints + that relate to the tasks, such as deadlines, maximum latency for data + to pass from one point in the computation to another, and quality + related information. Again, it is up to the language and plugin to + agree on what data is extracted, passed, and then used for scheduling. + Meanwhile, it is up to VMS to provide the services required by the + scheduler to make use of the information. + + As research progresses, additional types of information may become + necessary, so this flexibility from the plugin system will prove key. + \ The plugin plus VMS implementation are the hardware abstraction -- + the parallel equivalent of what the instruction set used to be for + sequential processors. \ The two define the behavior that the binary + expects to be present, so not only can the implementation of this + behavior evolve, but so can the behavior present and information + passed. + + This, finally, begs the + question: what kind of information and services must VMS provide to the + plugin? It must expose the features of the hardware that matter the + most to performance (computation, energy, and real-world related + performance). We suggest that the memory hierarchy and communication + between the memory pools are the most important features for parallel + performance. \ However, the VMS interface should only expose the + portions of memory affectable by a runtime scheduler (the register set + usage of a sequential processor is fixed by the binary and so not + exposed). + + We suggest that most parallel architectures will eventually fall into a + small number of classes, each of which exposes sufficient structure + without exposing chip-specific details. What's important is the type(s) + of cores, the pools of memory, and the nature of communication between + them. On communication, the scheduler can treat the network + statistically with relatively simple models, independently from the + topology, without undue loss of performance >. So the + main feature is coherent memory vs distributed, which determines + whether communication can take place by shared variables in the code vs + whether it needs explicit action. + + The second area of intense research will be determining the set of + interfaces to expose these hardware features such that the number of + plugins needed to get good performance on nearly all hardware is + minimized. We propose that most parallel hardware will fit into a + hierarchical combination of: 1) multi-core and many-core that share a + single coherent memory 2) one or more SIMD units that share a single + coherent memory 3) collections of those connected by shared memory 4) + distributed collections of those. Each memory pool, such as a cache or + scratchpad, is exposed, with the communication costs from each pool to + each other pool, and whether communication between them is automated or + explicit. Applying this to known architectures: single-socket + multi-core systems fall into 1, while adding a GPGPU adds a combination + of 2 and 4. \ The Cell BE is a combination of 1 and 4, as is the SCC. + \ Larrabee would have been in 1, 2, and 3 but may have been more + effectively treated as 1, 2, and 4. \ Traditional supercomputers made + up of shared-memory nodes connected by networks are combinations of 1 + and 4. + + This will be difficult research (some of which + is currently in progress) developing low-overhead schedulers that have + a single binary-interface, but efficiently handle a range of related + combinations of hardware features. An example would be a single plugin + that is efficient on various multi-core systems with GPU accelerators + -- independent of which particular multi-core chips, and independent of + which GPU chips. + + <\with|par-columns|1> + <\big-figure> + + + + + + + Figure 4 depicts how the pieces fit together. At the top, independent + software developers write applications, in a variety of languages. Each + language defines its own format for conveying task-related info. + Independently, plugins are implemented that accept that format, one + plugin for each hardware class. This allows hardware manufacturers to + supply their own plugins, for unusual hardware designs, and still take + advantage of the existing application binaries (non-standard + instruction sets also need an install-time translator). + + The plugins, in the middle, act as a cross-bar switch, connecting the + binaries to the hardware abstractions. They are separately distributed + and loaded onto the hardware, much the way device drivers are + currently. + + At the bottom, the hardware abstraction implementations standardize the + hardware. They are mainly supplied by the hardware manufacturers, but + open-source implementations will likely also arise. + + Note that the only software developed for a new HW platform is the + VMS-core abstraction, sequential C compiler, and a bare-bones OS (and + possibly a binary-optimizer that runs during installation or at + run-time, if the plugin defines an interface for such). Existing + applications are adpated via the plugin and abstraction. + + We expect that a small number of HW classes will quickly come to + dominate, which will encourage later HW development to fit within the + dominant classes. As a result, a standard set of sequential C compilers + will emerge, allowing software developers to perform a single + compilation pass. For fine tuning of compilation + choices, we expect install-time binary rewriters or run-time binary + optimizers. + + The end-result is that no centralized control is needed. Language + designers are free to innovate, inventing new parallelism constructs + and communication abstractions, and need as little as just the set of + plugins, or just the source-to-C translator to reach all the standard + hardware platforms. Likewise, hardware manufacturers are free to + innovate, needing minimal software development for a new chip to enjoy + access to all the applications. + + Note that new hardware still has the option of more aggressive binary + optimizers. These have richer application information available than + typical due to the task information bundled into the binary.\ + + The set of plugins is the key to this portability, in combination with + funnelling many applications to the same parallelism information at the + top, and funnelling many hardware platforms to the same abstraction at + the bottom. + + + + <\with|par-columns|2> + + + <\with|par-columns|2> + As far as a binary is concerned, the parallel behavior of the hardware + is represented by the combination of VMS plus the plugin, while the + \ sequential behavior of the hardware's processing-elements is + represented by the Instruction Set of each core. + + The VMS implementation is made up of a master virtual-processor that + receives and calls the plugin functions, and a ``core-controller'' that + handles transferring the physical-core between animating the master + virtual processor and animating the application's virtual processors, + but according to the decisions the plugin functions make, when called + by the master VP. As part of invoking a parallelism construct, an + application VP attaches to itself a request destined for the master VP, + then suspends. We next review how this request reaches the plugin's + parallelism-construct implementation, called the requestion handler, by + walking through the steps VMS takes during operation. + + The steps of operation are numbered in + Figure . \ Taking them in order, 1) + scans the scheduling slots to see which ones' + slaves have suspended since the previous scan. \ 2) It hands these to + the request handler plugged-in. \ \ 3) The data in the request causes + manipulation of the data structures within the semantic state. \ These + structures hold all the slaves currently in the blocked state. \ 4) + Requests cause slaves to be moved to the ready-container, which was + implemented as an array of simple queues, one to each physical core. + Which core receives the slave is under plugin control, determined by a + combination of request contents, semantic state and physical state. 5) + During the scan, the also looks for empty slots. + It calls the scheduler plug-in function, which chooses a slave from the + ready container. \ 6) The then places the slave + VP's pointer into the scheduling slot, making it available to the + . \ 7) When done with the scan, + suspends, switching animation back to the . \ 8) + takes slave VPs out of the slots, then 9) switches + animation to them. \ 10) When a slave self-suspends, animation returns + to the , which picks another, until 11) all slots + are empty and the switches animation to the + . + + <\with|par-first|0fn> + <\with|par-left|0cm> + + + + + Internal elements of VMS + implementation > + + All of that happens on each core separately, but in this + particular implementation we use a central to + ensure that only one core's can be active at any + time. \ This guarantees non-overlap of trace-segments from different + s, allowing the plugins to use sequential + algorithms, without a performance penalty. + + + + + We implemented blocked dense matrix multiply and ran on + a Core2Quad 2.4Ghz chip. + + As shown in Table 1, time to implement + the runtime for the three parallel libraries averages 2 days. As an + example of productivity, adding nested transactions, parallel singleton, + and atomic function-execution to SSR required a single afternoon, + totaling less than 100 lines of C code. + + |||||||>||||>||||>||||>||||>>>>|Person-days + to design, code, and test the library plus plug-in of each language, in + the order attempted. L.O.C. is lines of (original) code, excluding + libraries and comments.>>>>>> + + \ seen in Table + . + + The code has not been designed for speed, but rather to be easy to + understand and modify. In particular, the schedulers are simple queues + with no optimization for performance. + + <\with|par-mode|left> + |||||||||||||||>||||>|>|||>||||>||||>||||>||||>||||>||||>||||>||||>||||>||||>||||>||||>||||>||||>||||>>>>|Cycles of overhead, per scheduled + slave, consisting of: A) VMS-only cycles spent in VMS portion of + , B) time in the to switch + between VPs, C) Language-specific cycles spent in the plugin's Request + Handler and Scheduler, and D) obtaining the Master lock. \ ``comp + only'' column is cycles with perfect memory, ``comp + mem'' is actual + cycles. ``Plugin-concur'' is only concurrency related requests, + ``plugin-all'' includes create and malloc requests. Numbers are to two + significant digits due to variability. \ Language overhead was measured + while running Matrix Multiply.>>>>>> + + + We compare our implementation of the + and constructs against the distributed + version of Cilk, in Table , which shows + that the same application code has similar performance. + + ||||||||||||||||>|||>|||>|||>|||>|||>|||>|||>|||>>>>|Head-to-head + comparison of exe time in seconds for VCilk vs Cilk 5.4 on MM. \ VCilk + does 23% worse on large matrices that run for several seconds, but 210% + better on small matrices requiring milliseconds.>>>>>> + + \; + + Versus pthreads, our VMS based implementation has more than an order of + magnitude better overhead per invocation of mutex or condition variable + functionality, as seen in Table . + + <\with|par-mode|left> + |||||||||||||||||>|||||>|||||>|||||>|||||>|||||>|||||>>>>|Rough + measurements of cycles to perform synchronization primitives. \ For + VPThread, the first column shows computation time of plugin when all + memory accesses hit in the cache. The second column is total time, + including , , and the effects + of cache and page misses. Pthread times are deduced from round-trip + experiments. The ratio calculations are pthread vs total + VPThread.>>>>>> + + + Conclusion> + + This is a position paper, merely a suggestion for a large scale + organizing principle by which real-world entities can cooperatively + achieve performance portability. The key pattern is the funnelling of + many applications to the same parallelism information at the top, the + funnelling of many hardware platforms to the same abstraction at the + bottom, and the set of plugins that connect the two ends. + + + <\bibliography|bib|Helpers/plain|Helpers/Bib_for_papers.bib> + \; + + + \; + + \; + + +<\initial> + <\collection> + + + + + + + + + + + + + + +<\references> + <\collection> + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + + + +<\auxiliary> + <\collection> + <\associate|bib> + Hewitt10 + + Actors97 + + ComponentModel00 + + hoare78 + + milner99 + + Gelernter85Linda + + <\associate|figure> + > + + <\tuple|normal> + \; + + The toolchain is split, the top portion is related to parallelism and + the bottom portion does sequential compilation of C code. In the top + box, source code is transformed into C code that has calls inserted. + They invoke the plugin, during the run, to perform parallelism + operations, such as synchronizations, sends, receives, publish, and + so on. The top box also extracts parallelism information from the + source, and encodes it as implementations of library calls. These are + later invoked by the plugin to retrieve the information. \ In this + way, the generated parallelism information passes through any + standard sequential C compiler, which is the only hardware-specific + portion. + > + + > + + Internal elements of VMS + implementation |> + + <\associate|table> + Person-days to design, code, and + test the library plus plug-in of each language, in the order attempted. + L.O.C. is lines of (original) code, excluding libraries and + comments.|> + + Cycles of overhead, per + scheduled slave, consisting of: A) VMS-only cycles spent in VMS portion + of |language||master_loop>, + B) time in the |language||core_loop> + to switch between VPs, C) Language-specific cycles spent in the + plugin's Request Handler and Scheduler, and D) obtaining the Master + lock. \ ``comp only'' column is cycles with perfect memory, ``comp + + mem'' is actual cycles. ``Plugin-concur'' is only concurrency related + requests, ``plugin-all'' includes create and malloc requests. Numbers + are to two significant digits due to variability. \ Language overhead + was measured while running Matrix Multiply.|> + + Head-to-head comparison of exe + time in seconds for VCilk vs Cilk 5.4 on MM. \ VCilk does 23% worse on + large matrices that run for several seconds, but 210% better on small + matrices requiring milliseconds.|> + + Rough measurements of cycles to + perform synchronization primitives. \ For VPThread, the first column + shows computation time of plugin when all memory accesses hit in the + cache. The second column is total time, including + |language||master_loop>, + |language||core_loop>, and + the effects of cache and page misses. Pthread times are deduced from + round-trip experiments. The ratio calculations are pthread vs total + VPThread.|> + + <\associate|toc> + |math-font-series||1Overview + and Motivation> |.>>>>|> + + + |math-font-series||2VMS> + |.>>>>|> + + + |2.1Overview of VMS + \ \ |.>>>>|> + > + + |math-font-series||3Specialization> + |.>>>>|> + + + |3.1Three-step specialization + |.>>>>|> + > + + |Isolating parallelism in the toolchain: + |.>>>>|> + > + + |Caveat: |.>>>>|> + > + + |What task information to extract: + |.>>>>|> + > + + |Info exposed by VMS to plugin: + |.>>>>|> + > + + |math-font-series||4Eco-System> + |.>>>>|> + + + |math-font-series||5> + |.>>>>|> + + + |5.1Internal Workings of VMS + |.>>>>|> + > + + |Steps of Operation: + |.>>>>|> + > + + |Enabling sequential implementation of + parallelism semantics: |.>>>>|> + > + + |math-font-series||6Performance> + |.>>>>|> + + + |Setup: |.>>>>|> + > + + |Implementation-Time: + |.>>>>|> + > + + |Execution Performance: + |.>>>>|> + > + + |Head to Head: VCilk vs Cilk 5.4 \ plus + \ VPThread vs pthread: |.>>>>|> + > + + |math-font-series||7Conclusion> + |.>>>>|> + + + |math-font-series||Bibliography> + |.>>>>|> + + + + \ No newline at end of file diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/PStack/Eco_System/Jan_2011_Hotpar_Port_Perf_3.pdf Binary file 0__Papers/PStack/Eco_System/Jan_2011_Hotpar_Port_Perf_3.pdf has changed diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/PStack/Eco_System/Jan_2011_Hotpar_Port_Perf_3.tm --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/PStack/Eco_System/Jan_2011_Hotpar_Port_Perf_3.tm Sun Apr 08 09:00:10 2012 -0700 @@ -0,0 +1,965 @@ + + + + +<\body> + ||>||> + + <\abstract> + Performance portability, in the sense that a single source can run with + good performance across a wide variation of parallel hardware platforms, + is strongly desired by industry and actively being researched. \ However, + evidence is mounting that performance portability cannot be realized at + just the toolchain level, or just at the runtime level or just at the + hardware abstraction level. + + This is a position paper, making a suggestion for how the groups involved + can more efficiently solve the performance portability problem together. + We don't propose a solution, at all, but rather a support system for the + players to self organize and collectively find one. \ The support system + is based on a new virtualization mechanism called VMS + (Virtualized Master-Slave), that fulfills the needs of an organizing + principle, and provides focus that may increase research efficiency. The + difficult work will be the on-going research efforts on parallel language + design, compilers, source-to-source transform tools, binary optimization, + run-time schedulers, and hardware support for parallelism. \ Although it + doesn't in itself solve the problem, such an organizing principle may be + a valuable step towards a solution -- the problem may be too complex and + require cooperation of too many real-world entities for a single-entity + solution. + + We briefly review VMS, and illustrate how it could be used to give rise + to an eco-system in which performance portability is collectively + realized. \ To support the suggestion, we give measurements of the time + to implement three parallelism-construct libraries, and performance + numbers for them, along with measurements of the basic overhead of VMS. + + + <\with|par-columns|1> + <\with|par-columns|2> + + + Evidence is mounting that one-stop solutions to performance portability + fail to address critical real-world patterns. For example, attempting + to place the full specialization into the toolchain centralizes the + specialization effort in a single organization. One route is PetaBricks + style which places specialization into a single + tool that injects an adaptable runtime. Another is BLIS style + which automates re-compilation for new targets and + automates distribution of multiple binaries -- to do this for thousands + of different software development entities requires centralization. + Either way, such a centralized approach concentrates control, creates a + choke-point slowing the pace of innovation, and has serious unresolved + technical challenges. + + Pure runtime based approaches imply a single binary, + with only the runtime dynamic-library changing across targets. This + frees hardware manufacturers to independently deploy runtime libraries. + However, for performance they must take advantage of language-specific + constructs. This forces a separate runtime for each language. Without a + means to simplify the creation of such runtimes, and reuse effort + across hardware, this represents significant development effort. + + Finally, hardware abstraction based approaches, such as JITs + or VMMs , place the + work of specializing into the virtual machine, which makes reuse + difficult, forcing rewrite of JIT internals for each hardware platform, + for each language. This software cost is an issue in the embedded space + where new hardware is introduced often and has a limited market size to + amortize the software cost. \ In addition, this one-stop approach + requires a different JIT for each language, because it has to recognize + language-specific features to specialize -- or else it fails to achieve + good performance. This requires extensive work, making domain-specific + languages time-consuming and difficult to develop, and the multiple + JITs logistically awkward. + + In practice, most approaches combine at least two in a limited way. We + take the position in this paper that a support system is needed that + operates at all three levels: the language design plus toolchain level; + the runtime system level; and the hardware abstraction level. Sequoia + does this, in a limited way. \ We propose a more + general approach that supports (multiple) languages without restricting + them, has more freedom to specialize the runtime, \ and reduces the + effort to add new target hardware. It takes advantage of VMS + (Virtualized Master-Slave) , which + provides pieces for each level, acting as an organizing principle. + + Section 2 reviews VMS. Section 3 reviews performance portability + fundamentals. Section 4 illustrates using VMS to support an eco-system. + Section 5 gives details of a VMS implementation, and 6 gives VMS + performance. Section 7 concludes. + + + + On nomenclature, in this paper we define as a 3-tuple: + \animation event, collection of code animated, collection of + information the code is animated upon\. The phrase ``we create a + task'' means we create a combination of code plus data with the intent + to animate. + + Virtualized Master Slave (VMS) is an virtualization + mechanism that replaces Threads. \ Each language has its own scheduler, + along with a definition of parallelism constructs, such as + publish-subscribe channel, or send-receive, or spawn-sync. This + scheduler plus parallelism construct implementation are plugged in to + VMS, and, together, complete the runtime for the language. + + The plugin is separately loaded onto the hardware as a + dynamic library or device driver. This makes the plugin a new component + in the software stack. + + The VMS model can be implemented as a user-space library, or existing + OS kernels can be converted to the VMS model by opening up their + scheduler, exposing the VMS plugin interface. The parallelism + constructs are implemented using sequential algorithms, reducing + implementation time for parallelism semantics to a matter of days. + \ The plugged-in scheduler gives the language control over assigning + work to physical cores. On multi-core shared-memory machines, the + run-time overhead is low, around a few hundred nano-seconds per + concurrency operation. + + VMS isn't a language, but rather the creation of language + runtimes. Examples could include: Actors + ; Components ; + process calculi like CSP and Pi-calculus + ; and coordination languages like Linda + . \ Systems like TBB, + OpenMP, and Sequoia may also be implemented with VMS, + as well as the threading portion of Java, and even pthreads. + + + + Portable performance is achieved by specializing the source code to the + hardware. \ For traditional sequential source on sequential processors, + the specialization was the translation to machine code and optimization + that took place in the compiler. + + This one-step specialization was sufficient because most of the + performance portability was provided by using micro-architecture + hardware techniques that exploited instruction-level parallelism + underneath a standard instruction-set abstraction (plus faster clock). + + We conjecture that the reason such a hardware-based approach to + performance portability has failed for parallel hardware is that larger + granularity parallelism is tied to the language constructs and to + application constructs (whereas instruction-level parallelism is tied + only to the machine-instruction-set constructs). Hence, information + about the language patterns and application patterns must be available + in order to exploit these larger granularities. + + Following this intuition, we propose that a system for parallel + performance portability have a means to identify language and + application constructs and package this information into a standard + format. \ Also, a hardware abstraction should be provided that accepts + such information and uses it to make high-quality decisions about task + creation, sizing, and placement. + + + + VMS fits this proposal by making specialization happen in three steps, + as illustrated in Figure 1. + + First, in the top box, the toolchain extracts task information useful + to the scheduler and packages it into the binary. \ This specializes + the source to the plugin's interface. \ Second, in the middle, the + scheduler in the plugin retrieves the info and uses it to make + scheduling decisions. This is specializing the binary to the hardware + abstraction. Third, at the bottom, the VMS-core implementation hides + hardware details behind the interface. This is specializing the + hardware abstraction to the hardware. + + <\with|par-first|0fn> + |Specialization + occurs in three places. > + + + The combination of plugin plus VMS has the same function that the + instruction set had back in the sequential days -- it provides a + standard hardware abstraction. \ VMS has the advantage that the + abstraction can be chosen separately for each binary, by choosing the + plugin. + + Focusing on the + toolchain, we propose breaking it into two sections: one for + parallelism, the other for sequential. The parallelism portion extracts + the task and language information needed to make high quality + scheduling decisions. \ The sequential specializes individual functions + to the sequential cores. \ The parallelism portion remains constant + across hardware, only the sequential portion changes when the + instruction-set of the target hardware changes (in effect, this moves a + portion of the compiler into an install-time, or load-time, or run-time + component that completes binary specialization). + + One possible way to achieve this is to make the parallel portion + transform the original source to C code, with embedded calls to the + parallelism constructs. Also during this source-to-C-plus-lib-call + transform, the task information is packaged into functions in some way. + \ The resulting C-plus-lib-calls source is then compiled with a + sequential C compiler to make a binary, as depicted in Figure 2. + + <\with|par-first|0fn> + <\small-figure|> + \; + + The toolchain is split into parallel and sequential portions. The + parallel portion generates the bodies of information-carrying + functions that the plugin later calls to retrieve the info. + + + + Meanwhile, the plugins for that language know the names of the library + functions the task information has been packaged into. \ Hence, when + the binary is linked to a plugin at load time, the task-info functions + within the binary become available to the plugin. \ They are called + during the run to extract the information. + + This scheme allows unmodified sequential compilers to be used to pass + the information along, inside of a standard binary format. \ It also + separates the parallel and sequential portions of the tool chain + cleanly, so only the relatively simple sequential C compiler changes + with hardware. \ This scheme also leaves the language designers in + charge of deciding the nature and definition of the information + carrying functions. + + These properties enable reuse of the same parallel portion of the + toolchain across chips, which is especially valuable in the embedded + market. \ With the inclusion of real-time aspects, such as latency + bounds and deadlines, this could dramatically speed up time to market + and reduce cost of introduction of new embedded chips. + + This part of the proposal may run into + difficulties in practice. The details of architectures like vector + units and GPUs are too fine-grain for typical run-time scheduling, and + may require multi-versioned binaries or + binary optimizers or PetaBricks style + adaptability. It will require extensive toolchain research by many + groups to either solve this or give reasonable evidence that it's not + practical. + + This begs the question: + what kind of task information is sufficient for performance portability + across the array of foreseeable parallel architectures? Fortunately, + the support system doesn't define this, but leaves it free to evolve as + research progresses, enabling an upgrade path. + + We propose three kinds of information will be sufficient: 1) + manipulators, which are able to modify the size of tasks, choose among + alternative binary versions, and change the data layout and access + pattern (such as auto-tuners injected into the binary and invoked by + plugin), 2) information about the tasks such as communication with + other tasks (for data affinity), preferred core type, data footprint, + and predicted execution time, and 3) real-world constraints that relate + to the tasks, such as deadlines, maximum latency for data to pass from + one point in the computation to another, and quality related + information. Again, it is up to the language and plugin to agree on + what data is extracted, passed, and then used for scheduling. + Meanwhile, VMS must provide the scheduler with the services needed to + make use of that data. + + As research progresses, additional types of information may prove + needed, so flexibility from the plugin system will be key. \ The plugin + plus VMS implementation are a hardware abstraction -- the parallel + equivalent of what the instruction set used to be for sequential + processors, but now defined in software. + + This, finally, begs the + question: what kind of information and services must VMS provide to the + plugin? It must expose the structure of the hardware that matters most + to performance (computation, energy, and real-world related + performance). + + \ We believe that the type(s) of cores, the pools of memory and + communication between them are the most important features for parallel + performance. However, it should only expose the portions of memory + affectable by a runtime scheduler (the register set usage of a + sequential processor or vector processor is fixed by the binary and so + not exposed). + + On the nature of communication, we believe that the scheduler can + safely model any network with a topology-independent statistical model, + without undue loss of performance . This + leaves the main feature as coherent memory vs distributed, which + determines whether communication takes place by shared variables in the + code vs whether it needs explicit action. + + Following this, we propose that for the purposes of scheduling, most + parallel hardware will be adequately modeled by a simplified + hierarchical graph. Nodes are of type: 1) physical memory array, 2) + processor pipeline, 3) internally-scheduled sub-graph. Communication + links are chosen from: 1) automated movement (ex: due to coherence + mechanism) 2) explicit movement. \ The links are statistical models of + how well the physical network moves data. + + The internally-scheduled sub-graph is the key feature. \ It allows an + entire GPU, for example, to be treated as one run-time schedulable node + as StarPU does. It also allows a hierarchy of plugins + to exist for complex hardware. Higher level plugins schedule large + tasks to sub-graphs, in which the tasks are again divided (using + manipulators packaged by the toolchain, such as demonstrated by + PetaBricks and DKU). Techniques + such as Hierarchically Tiled Arrays and the loop + manipulation features of the X Language will also + facilitate such hierarchical scheduling. + + We suggest that most parallel architectures will eventually fall into a + small number of groups. All targets in a group have similar graphs. + This conveys sufficient structure to efficiently schedule any target in + the group, without exposing chip-specific details. + + This will be difficult research (some of which + is currently in progress) developing low-overhead schedulers that have + a single binary-interface, but efficiently handle a range of related + hardware graphs. An example would be a single plugin whose scheduler is + efficient on various multi-core systems with GPU accelerators, + regardless of which particular multi-core and GPU chips are present, + possibly adapting job-scheduling approaches . + + + + Figure 4 depicts how many real-world entities might interact to supply + the various pieces. At the top, independent software developers write + applications, in a variety of languages. Each language is defined by a + research group, along with its own format for conveying task-related + info.\ + + The plugins, in the middle, act as a cross-bar switch, connecting the + binaries to the hardware abstractions. They are separately distributed + and loaded onto the hardware, and separately written. The middle will + fill out as research teams discover scheduling techniques for various + groupings (classes) of hardware. Each implements a plugin for a + hardware class, which accepts a particular language's format. For + unusual hardware designs, the manufacturer supplies their own plugin + for the popular languages, thereby taking advantage of the existing + application binaries (non-standard instruction sets also need an + install-time translator). + + At the bottom, the VMS-core implementations standardize the hardware. + They are mainly supplied by the hardware manufacturers. + + The minimal software needed for a new HW platform is the VMS-core + abstraction, sequential C compiler, and a bare-bones OS (and possibly a + binary-optimizer). Existing applications are adapted via the plugins + for the hardware class and the abstraction. + + We expect that a small number of HW classes will quickly come to + dominate, which will encourage later HW development to fit within the + dominant classes. As a result, a standard set of plugins, and + sequential C compilers will emerge, allowing software developers to + perform a single compilation pass. For fine tuning of + compilation choices (or optimization of fine-grain hardware like SIMD + GPUs), we expect install-time binary re-writers or run-time binary + optimizers. + + The end-result is that no centralized control is needed. Language + designers innovate, inventing new parallelism constructs, and need as + little as just a source-to-C translator to reach all the standard + hardware platforms. Likewise, hardware manufacturers innovate freely, + needing minimal software development for a new chip to enjoy access to + existing development tools and applications. + + Note that new hardware still has the option of aggressive binary + optimizers. In this scheme they have richer application information + available than normal due to the task information bundled into the + binary.\ + + The set of plugins is the key to this portability, in combination with + funneling many applications to the same parallelism information at the + top, and funneling many hardware platforms to similar graphs at the + bottom. + + <\with|par-columns|1> + <\big-figure> + + + + + + + <\with|par-columns|2> + + + <\with|par-columns|2> + To give greater understanding of VMS, we describe the internal working + of our implementation for shared-memory multi-core hardware. It has a + master virtual-processor (VP) on each core, into which the plugins are + inserted, and a ``core-controller'' that handles transferring the + physical-core between animating the master VP and animating the slave + VPs. The plugin functions are called by the master VP and control which + slave goes to which core (more detail shortly). All application code is + animated by slave VPs. When app-code invokes a parallelism construct, + the slave VP first attaches to itself a request representing the + parallelism construct (and destined for the plugin in the master VP) + then suspends. We next review how this request reaches the plugin's + parallelism-construct implementation, called the , + by walking through the steps VMS takes during operation. + + The steps of operation are numbered in + Figure . \ Taking them in order, 1) + scans the scheduling slots to see which ones' + slaves have suspended since the previous scan. \ 2) It hands these to + the request handler plugged-in. \ \ 3) The data in the request causes + the request handler to manipulate data structures within the shared + semantic state. \ These structures hold all the slaves currently + suspended. \ 4) Requests cause slaves to be moved to the ready + container (for SSR, this is one queue, readyQ, on each physical core -- + SSR constructs and work-stealing determine which core a slave is + assigned to). 5) During the scan, the + additionally looks for empty slots. For each, it calls the scheduler + plug-in function, which returns a slave (for SSR, this just pops the + Q). \ 6) The then places the slave VP's pointer + into the scheduling slot, making it available to the + . \ 7) When done with the scan, + suspends, switching animation back to the . \ 8) + takes slave VPs out of the slots, then 9) switches + animation to them. \ 10) When a slave self-suspends (due to app-code), + animation returns to the , which picks another, + until 11) all slots are empty and the again + switches animation to the . + + <\with|par-first|0fn> + <\with|par-left|0cm> + + + + + Internal elements of VMS + implementation > + + In this + particular implementation we use a central to + ensure that only one core's can be active at any + time. \ This guarantees non-overlap of s on + different cores, allowing the plugins to use sequential algorithms. + + + + + We implemented blocked dense matrix multiply and ran on + a Core2Quad 2.4Ghz chip. + + As shown in Table 1, time to implement + the three parallel libraries averages 2 days. As an example of + productivity, adding nested transactions, parallel singleton, and atomic + function-execution to SSR required a single afternoon, totaling less than + 100 lines of C code. + + |||||||>||||>||||>||||>||||>>>>|Person-days + to design, code, and test each parallelism library, in the order + attempted. L.O.C. is lines of (original) code, excluding libraries and + comments.>>>>>> + + \ Performance of VMS is seen in Table + . The code has not been designed for speed, + but rather to be easy to understand and modify. In particular, the + schedulers are simple queues with no optimization for performance. + + <\with|par-mode|left> + ||||||||||||||>||||>|>|||>||||>||||>||||>||||>||||>||||>||||>||||>||||>||||>||||>||||>>>>|Cycles of + overhead, per scheduled slave. ``comp only'' is perfect memory, ``comp + + mem'' is actual cycles. ``Plugin-concur'' only concurrency requests, + ``plugin-all'' includes create and malloc requests. Two significant + digits due to variability.>>>>>> + + + Comparing our implementation of the + and constructs against the distributed + version of Cilk, the same application code has similar performance. VCilk + does 23% worse on large matrices that run for several seconds, but 210% + better on small matrices requiring only milliseconds. Versus pthreads, + our VMS based implementation has more than an order of magnitude better + overhead per invocation of mutex or condition variable functionality. + + Conclusion> + + This is a position paper, merely a suggestion for a support system for + cooperatively achieving performance portability. The key pattern is the + funneling of many applications to the same parallelism information at the + top, the funneling of many hardware platforms to the same abstraction at + the bottom, and the set of plugins that connect the two ends. + + + <\bibliography|bib|Helpers/plain|Helpers/Bib_for_papers.bib> + <\bib-list|10> + DKU-ized Deblocking Filter code. + http://dku.svn.sourceforge.net/viewvc/dku/branches/DKU_C__Deblocking__orig/. + + Anant Agarwal. Limits on + interconnection network performance. + , 2:398 -- 412, 1991. + + G.Agha, I.Mason, + S.Smith, and C.Talcott. A foundation for actor + computation. , 7(01):1--72, 1997. + + K.Aida, A.Takefusa, + H.Nakada, S.Matsuoka, S.Sekiguchi, and + U.Nagashima. Performance evaluation model for + scheduling in global computing systems. + , 14:268--279, 2000. + + Jason Ansel, CyChan, + YeeLok Wong, Marek Olszewski, Qin Zhao, Alan Edelman, and Saman + Amarasinghe. Petabricks: a language and compiler for + algorithmic choice. In , PLDI '09, pages 38--49, 2009. + + Cédric Augonnet, Samuel Thibault, + Raymond Namyst, and Pierre-André Wacrenier. StarPU: A + unified platform for task scheduling on heterogeneous multicore + architectures. In , Lecture Notes in Computer Science, pages + 863--874. 2009. + + B.Catanzaro, S.Kamil, + Y.Lee, K.Asanovic, J.Demmel, K.Keutzer, + J.Shalf, K.Yelick, and A.Fox. Sejits: + Getting productivity and performance with selective embedded jit + specialization. , 2009. + + Charles Consel. A general + approach for run-time specialization and its application to c. + pages 145--156. ACM Press, 1996. + + Intel Corp. TBB home page. + http://www.threadingbuildingblocks.org. + + Sebastien Donadio, James Brodman, + Thomas Roeder, Kamen Yotov, Denis Barthou, Albert Cohen, María + Garzarán, David Padua, and Keshav Pingali. A language for + the compact representation of multiple program versions. In + , Lecture Notes in Computer Science, pages 136--151. 2006. + + EDuesterwald. + Design and engineering of a dynamic binary optimizer. + , 93:436 -- + 448, 2005. + + Kayvon Fatahalian, DanielReiter + Horn, TimothyJ. Knight, Larkhoon Leem, Mike Houston, + JiYoung Park, Mattan Erez, Manman Ren, Alex Aiken, + WilliamJ. Dally, and Pat Hanrahan. Sequoia: programming + the memory hierarchy. In , + page83, 2006. + + Grigori Fursin, Albert Cohen, Michael + O’Boyle, and Olivier Temam. A practical method for quickly + evaluating program optimizations. In Tom Conte, Nacho + Navarro, Wen-mei Hwu, Mateo Valero, and Theo Ungerer, editors, + , Lecture Notes in Computer Science, pages 29--46. Springer + Berlin / Heidelberg, 2005. + + Jörn Gehring and Friedhelm Ramme. + Architecture-independent request-scheduling with tight + waiting-time estimations. In , volume 1162 of + , pages + 65--88. 1996. + + D.Gelernter. + Generative communication in Linda. + , 7(1):80--112, 1985. + + Jia Guo, Ganesh Bikshandi, + BasilioB. Fraguela, MariaJ. Garzaran, and David Padua. + Programming with tiles. In + , PPoPP '08, pages + 111--122, 2008. + + Sean Halle. VMS home page. + http://vmsexemodel.sourceforge.net. + + Sean Halle and Albert Cohen. + An extensible virtualization mechanism to replace threads. + submitted to PLDI 2011. + + Sean Halle and Albert Cohen. + Dku pattern for performance portable parallel software, 2009. + http://www.soe.ucsc.edu/share/technical-reports/2009/ucsc-soe-09-06.pdf. + + Sean Halle and Albert Cohen. + Leveraging semantics attached to function calls to isolate + applications from hardware. In , June 2010. + + Carl Hewitt. Actor model of + computation, 2010. http://arxiv.org/abs/1008.1459. + + C.A.R. Hoare. + Communicating sequential processes. + , + 21(8):666--677, 1978. + + GLeavens and + MSitaraman (eds). . Cambridge University Press, + 2000. + + Robin Milner. + . Cambridge University Press, 1999. + + OpenMP organization. + OpenMP home page. http://www.openmp.org. + + M.Rosenblum and + T.Garfinkel. Virtual machine monitors: current + technology and future trends. , 38:39 -- 47, 2005. + + Ajeet Shankar, S.Subramanya + Sastry, Rastislav Bodík, and JamesE. Smith. Runtime + specialization with optimistic heap analysis. In + , OOPSLA '05, pages 327--343, 2005. + + Xiaolan Zhang, Zheng Wang, Nicholas + Gloy, J.Bradley Chen, and MichaelD. Smith. System + support for automatic profiling and optimization. In + , SOSP '97, pages 15--26, 1997. + + + + \; + + \; + + +<\initial> + <\collection> + + + + + + + + + + + + + + +<\references> + <\collection> + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + + + +<\auxiliary> + <\collection> + <\associate|bib> + PetaBricks09 + + BLISInHotPar + + DKUTechRep + + Sejits + + Shankar05 + + Rosenblum05 + + Sequoia06 + + VMSSubmitted + + VMSHome + + Hewitt10 + + Actors97 + + ComponentModel00 + + hoare78 + + milner99 + + Gelernter85Linda + + TBBHome + + OpenMPHome + + Fursin05 + + Consel96 + + Duesterwald05 + + Zhang97 + + Agarwal91 + + Aida00 + + Augonnet09 + + DKUTechRep + + DeblockingCode + + Padua08 + + Donadio06 + + Gehring96 + + <\associate|figure> + > + + <\tuple|normal> + \; + + The toolchain is split into parallel and sequential portions. The + parallel portion generates the bodies of information-carrying + functions that the plugin later calls to retrieve the info. + > + + > + + Internal elements of VMS + implementation |> + + <\associate|table> + Person-days to design, code, and + test each parallelism library, in the order attempted. L.O.C. is lines + of (original) code, excluding libraries and + comments.|> + + Cycles of overhead, per + scheduled slave. ``comp only'' is perfect memory, ``comp + mem'' is + actual cycles. ``Plugin-concur'' only concurrency requests, + ``plugin-all'' includes create and malloc requests. Two significant + digits due to variability.|> + + <\associate|toc> + |math-font-series||1Overview + and Motivation> |.>>>>|> + + + |math-font-series||2Overview + of VMS> |.>>>>|> + + + |math-font-series||3Specialization> + |.>>>>|> + + + |3.1Three-step specialization + |.>>>>|> + > + + |Isolating parallelism in the toolchain: + |.>>>>|> + > + + |Focus Area: + |.>>>>|> + > + + |What task information to extract: + |.>>>>|> + > + + |Info exposed by VMS to plugin: + |.>>>>|> + > + + |Focus Area: + |.>>>>|> + > + + |math-font-series||4Eco-System> + |.>>>>|> + + + |math-font-series||5Internal + Workings of VMS> |.>>>>|> + + + |Steps of Operation: + |.>>>>|> + > + + |Sequential implementation of parallel + constructs: |.>>>>|> + > + + |math-font-series||6VMS + Measurements> |.>>>>|> + + + |Setup: |.>>>>|> + > + + |Implementation-Time: + |.>>>>|> + > + + |Execution Performance: + |.>>>>|> + > + + |Head to Head: + |.>>>>|> + > + + |math-font-series||7Conclusion> + |.>>>>|> + + + |math-font-series||Bibliography> + |.>>>>|> + + + + \ No newline at end of file diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/PStack/Eco_System/Jan_2011_Hotpar_Port_Perf_final.pdf Binary file 0__Papers/PStack/Eco_System/Jan_2011_Hotpar_Port_Perf_final.pdf has changed diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/PStack/Eco_System/Jan_2011_Hotpar_Port_Perf_final.tm --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/PStack/Eco_System/Jan_2011_Hotpar_Port_Perf_final.tm Sun Apr 08 09:00:10 2012 -0700 @@ -0,0 +1,965 @@ + + + + +<\body> + ||>||> + + <\abstract> + Performance portability, in the sense that a single source can run with + good performance across a wide variation of parallel hardware platforms, + is strongly desired by industry and actively being researched. \ However, + evidence is mounting that performance portability cannot be realized at + just the toolchain level, or just at the runtime level or just at the + hardware abstraction level. + + This is a position paper, making a suggestion for how the groups involved + can more efficiently solve the performance portability problem together. + We don't propose a solution, at all, but rather a support system for the + players to self organize and collectively find one. \ The support system + is based on a new virtualization mechanism called VMS + (Virtualized Master-Slave), that fulfills the needs of an organizing + principle, and provides focus that may increase research efficiency. The + difficult work will be the on-going research efforts on parallel language + design, compilers, source-to-source transform tools, binary optimization, + run-time schedulers, and hardware support for parallelism. \ Although it + doesn't in itself solve the problem, such an organizing principle may be + a valuable step towards a solution -- the problem may be too complex and + require cooperation of too many real-world entities for a single-entity + solution. + + We briefly review VMS, and illustrate how it could be used to give rise + to an eco-system in which performance portability is collectively + realized. \ To support the suggestion, we give measurements of the time + to implement three parallelism-construct libraries, and performance + numbers for them, along with measurements of the basic overhead of VMS. + + + <\with|par-columns|1> + <\with|par-columns|2> + + + Evidence is mounting that one-stop solutions to performance portability + fail to address critical real-world patterns. For example, attempting + to place the full specialization into the toolchain centralizes the + specialization effort in a single organization. One route is PetaBricks + style which places specialization into a single + tool that injects an adaptable runtime. Another is BLIS style + which automates re-compilation for new targets and + automates distribution of multiple binaries -- to do this for thousands + of different software development entities requires centralization. + Either way, such a centralized approach concentrates control, creates a + choke-point slowing the pace of innovation, and has serious unresolved + technical challenges. + + Pure runtime based approaches imply a single binary, + with only the runtime dynamic-library changing across targets. This + frees hardware manufacturers to independently deploy runtime libraries. + However, for performance they must take advantage of language-specific + constructs. This forces a separate runtime for each language. Without a + means to simplify the creation of such runtimes, and reuse effort + across hardware, this represents significant development effort. + + Finally, hardware abstraction based approaches, such as JITs + or VMMs , place the + work of specializing into the virtual machine, which makes reuse + difficult, forcing rewrite of JIT internals for each hardware platform, + for each language. This software cost is an issue in the embedded space + where new hardware is introduced often and has a limited market size to + amortize the software cost. \ In addition, this one-stop approach + requires a different JIT for each language, because it has to recognize + language-specific features to specialize -- or else it fails to achieve + good performance. This requires extensive work, making domain-specific + languages time-consuming and difficult to develop, and the multiple + JITs logistically awkward. + + In practice, most approaches combine at least two in a limited way. We + take the position in this paper that a support system is needed that + operates at all three levels: the language design plus toolchain level; + the runtime system level; and the hardware abstraction level. Sequoia + does this, in a limited way. \ We propose a more + general approach that supports (multiple) languages without restricting + them, has more freedom to specialize the runtime, \ and reduces the + effort to add new target hardware. It takes advantage of VMS + (Virtualized Master-Slave) , which + provides pieces for each level, acting as an organizing principle. + + Section 2 reviews VMS. Section 3 reviews performance portability + fundamentals. Section 4 illustrates using VMS to support an eco-system. + Section 5 gives details of a VMS implementation, and 6 gives VMS + performance. Section 7 concludes. + + + + On nomenclature, in this paper we define as a 3-tuple: + \animation event, collection of code animated, collection of + information the code is animated upon\. The phrase ``we create a + task'' means we create a combination of code plus data with the intent + to animate. + + Virtualized Master Slave (VMS) is an virtualization + mechanism that replaces Threads. \ Each language has its own scheduler, + along with a definition of parallelism constructs, such as + publish-subscribe channel, or send-receive, or spawn-sync. This + scheduler plus parallelism construct implementation are plugged in to + VMS, and, together, complete the runtime for the language. + + The plugin is separately loaded onto the hardware as a + dynamic library or device driver. This makes the plugin a new component + in the software stack. + + The VMS model can be implemented as a user-space library, or existing + OS kernels can be converted to the VMS model by opening up their + scheduler, exposing the VMS plugin interface. The parallelism + constructs are implemented using sequential algorithms, reducing + implementation time for parallelism semantics to a matter of days. + \ The plugged-in scheduler gives the language control over assigning + work to physical cores. On multi-core shared-memory machines, the + run-time overhead is low, around a few hundred nano-seconds per + concurrency operation. + + VMS isn't a language, but rather the creation of language + runtimes. Examples could include: Actors + ; Components ; + process calculi like CSP and Pi-calculus + ; and coordination languages like Linda + . \ Systems like TBB, + OpenMP, and Sequoia may also be implemented with VMS, + as well as the threading portion of Java, and even pthreads. + + + + Portable performance is achieved by specializing the source code to the + hardware. \ For traditional sequential source on sequential processors, + the specialization was the translation to machine code and optimization + that took place in the compiler. + + This one-step specialization was sufficient because most of the + performance portability was provided by using micro-architecture + hardware techniques that exploited instruction-level parallelism + underneath a standard instruction-set abstraction (plus faster clock). + + We conjecture that the reason such a hardware-based approach to + performance portability has failed for parallel hardware is that larger + granularity parallelism is tied to the language constructs and to + application constructs (whereas instruction-level parallelism is tied + only to the machine-instruction-set constructs). Hence, information + about the language patterns and application patterns must be available + in order to exploit these larger granularities. + + Following this intuition, we propose that a system for parallel + performance portability have a means to identify language and + application constructs and package this information into a standard + format. \ Also, a hardware abstraction should be provided that accepts + such information and uses it to make high-quality decisions about task + creation, sizing, and placement. + + + + VMS fits this proposal by making specialization happen in three steps, + as illustrated in Figure 1. + + First, in the top box, the toolchain extracts task information useful + to the scheduler and packages it into the binary. \ This specializes + the source to the plugin's interface. \ Second, in the middle, the + scheduler in the plugin retrieves the info and uses it to make + scheduling decisions. This is specializing the binary to the hardware + abstraction. Third, at the bottom, the VMS-core implementation hides + hardware details behind the interface. This is specializing the + hardware abstraction to the hardware. + + <\with|par-first|0fn> + |Specialization + occurs in three places. > + + + The combination of plugin plus VMS has the same function that the + instruction set had back in the sequential days -- it provides a + standard hardware abstraction. \ VMS has the advantage that the + abstraction can be chosen separately for each binary, by choosing the + plugin. + + Focusing on the + toolchain, we propose breaking it into two sections: one for + parallelism, the other for sequential. The parallelism portion extracts + the task and language information needed to make high quality + scheduling decisions. \ The sequential specializes individual functions + to the sequential cores. \ The parallelism portion remains constant + across hardware, only the sequential portion changes when the + instruction-set of the target hardware changes (in effect, this moves a + portion of the compiler into an install-time, or load-time, or run-time + component that completes binary specialization). + + One possible way to achieve this is to make the parallel portion + transform the original source to C code, with embedded calls to the + parallelism constructs. Also during this source-to-C-plus-lib-call + transform, the task information is packaged into functions in some way. + \ The resulting C-plus-lib-calls source is then compiled with a + sequential C compiler to make a binary, as depicted in Figure 2. + + <\with|par-first|0fn> + <\small-figure|> + \; + + The toolchain is split into parallel and sequential portions. The + parallel portion generates the bodies of information-carrying + functions that the plugin later calls to retrieve the info. + + + + Meanwhile, the plugins for that language know the names of the library + functions the task information has been packaged into. \ Hence, when + the binary is linked to a plugin at load time, the task-info functions + within the binary become available to the plugin. \ They are called + during the run to extract the information. + + This scheme allows unmodified sequential compilers to be used to pass + the information along, inside of a standard binary format. \ It also + separates the parallel and sequential portions of the tool chain + cleanly, so only the relatively simple sequential C compiler changes + with hardware. \ This scheme also leaves the language designers in + charge of deciding the nature and definition of the information + carrying functions. + + These properties enable reuse of the same parallel portion of the + toolchain across chips, which is especially valuable in the embedded + market. \ With the inclusion of real-time aspects, such as latency + bounds and deadlines, this could dramatically speed up time to market + and reduce cost of introduction of new embedded chips. + + This part of the proposal may run into + difficulties in practice. The details of architectures like vector + units and GPUs are too fine-grain for typical run-time scheduling, and + may require multi-versioned binaries or + binary optimizers or PetaBricks style + adaptability. It will require extensive toolchain research by many + groups to either solve this or give reasonable evidence that it's not + practical. + + This begs the question: + what kind of task information is sufficient for performance portability + across the array of foreseeable parallel architectures? Fortunately, + the support system doesn't define this, but leaves it free to evolve as + research progresses, enabling an upgrade path. + + We propose three kinds of information will be sufficient: 1) + manipulators, which are able to modify the size of tasks, choose among + alternative binary versions, and change the data layout and access + pattern (such as auto-tuners injected into the binary and invoked by + plugin), 2) information about the tasks such as communication with + other tasks (for data affinity), preferred core type, data footprint, + and predicted execution time, and 3) real-world constraints that relate + to the tasks, such as deadlines, maximum latency for data to pass from + one point in the computation to another, and quality related + information. Again, it is up to the language and plugin to agree on + what data is extracted, passed, and then used for scheduling. + Meanwhile, VMS must provide the scheduler with the services needed to + make use of that data. + + As research progresses, additional types of information may prove + needed, so flexibility from the plugin system will be key. \ The plugin + plus VMS implementation are a hardware abstraction -- the parallel + equivalent of what the instruction set used to be for sequential + processors, but now defined in software. + + This, finally, begs the + question: what kind of information and services must VMS provide to the + plugin? It must expose the structure of the hardware that matters most + to performance (computation, energy, and real-world related + performance). + + \ We believe that the type(s) of cores, the pools of memory and + communication between them are the most important features for parallel + performance. However, it should only expose the portions of memory + affectable by a runtime scheduler (the register set usage of a + sequential processor or vector processor is fixed by the binary and so + not exposed). + + On the nature of communication, we believe that the scheduler can + safely model any network with a topology-independent statistical model, + without undue loss of performance . This + leaves the main feature as coherent memory vs distributed, which + determines whether communication takes place by shared variables in the + code vs whether it needs explicit action. + + Following this, we propose that for the purposes of scheduling, most + parallel hardware will be adequately modeled by a simplified + hierarchical graph. Nodes are of type: 1) physical memory array, 2) + processor pipeline, 3) internally-scheduled sub-graph. Communication + links are chosen from: 1) automated movement (ex: due to coherence + mechanism) 2) explicit movement. \ The links are statistical models of + how well the physical network moves data. + + The internally-scheduled sub-graph is the key feature. \ It allows an + entire GPU, for example, to be treated as one run-time schedulable node + as StarPU does. It also allows a hierarchy of plugins + to exist for complex hardware. Higher level plugins schedule large + tasks to sub-graphs, in which the tasks are again divided (using + manipulators packaged by the toolchain, such as demonstrated by + PetaBricks and DKU). Techniques + such as Hierarchically Tiled Arrays and the loop + manipulation features of the X Language will also + facilitate such hierarchical scheduling. + + We suggest that most parallel architectures will eventually fall into a + small number of groups. All targets in a group have similar graphs. + This conveys sufficient structure to efficiently schedule any target in + the group, without exposing chip-specific details. + + This will be difficult research (some of which + is currently in progress) developing low-overhead schedulers that have + a single binary-interface, but efficiently handle a range of related + hardware graphs. An example would be a single plugin whose scheduler is + efficient on various multi-core systems with GPU accelerators, + regardless of which particular multi-core and GPU chips are present, + possibly adapting job-scheduling approaches . + + + + Figure 4 depicts how many real-world entities might interact to supply + the various pieces. At the top, independent software developers write + applications, in a variety of languages. Each language is defined by a + research group, along with its own format for conveying task-related + info.\ + + The plugins, in the middle, act as a cross-bar switch, connecting the + binaries to the hardware abstractions. They are separately distributed + and loaded onto the hardware, and separately written. The middle will + fill out as research teams discover scheduling techniques for various + groupings (classes) of hardware. Each implements a plugin for a + hardware class, which accepts a particular language's format. For + unusual hardware designs, the manufacturer supplies their own plugin + for the popular languages, thereby taking advantage of the existing + application binaries (non-standard instruction sets also need an + install-time translator). + + At the bottom, the VMS-core implementations standardize the hardware. + They are mainly supplied by the hardware manufacturers. + + The minimal software needed for a new HW platform is the VMS-core + abstraction, sequential C compiler, and a bare-bones OS (and possibly a + binary-optimizer). Existing applications are adapted via the plugins + for the hardware class and the abstraction. + + We expect that a small number of HW classes will quickly come to + dominate, which will encourage later HW development to fit within the + dominant classes. As a result, a standard set of plugins, and + sequential C compilers will emerge, allowing software developers to + perform a single compilation pass. For fine tuning of + compilation choices (or optimization of fine-grain hardware like SIMD + GPUs), we expect install-time binary re-writers or run-time binary + optimizers. + + The end-result is that no centralized control is needed. Language + designers innovate, inventing new parallelism constructs, and need as + little as just a source-to-C translator to reach all the standard + hardware platforms. Likewise, hardware manufacturers innovate freely, + needing minimal software development for a new chip to enjoy access to + existing development tools and applications. + + Note that new hardware still has the option of aggressive binary + optimizers. In this scheme they have richer application information + available than normal due to the task information bundled into the + binary.\ + + The set of plugins is the key to this portability, in combination with + funneling many applications to the same parallelism information at the + top, and funneling many hardware platforms to similar graphs at the + bottom. + + <\with|par-columns|1> + <\big-figure> + + + + + + + <\with|par-columns|2> + + + <\with|par-columns|2> + To give greater understanding of VMS, we describe the internal working + of our implementation for shared-memory multi-core hardware. It has a + master virtual-processor (VP) on each core, into which the plugins are + inserted, and a ``core-controller'' that handles transferring the + physical-core between animating the master VP and animating the slave + VPs. The plugin functions are called by the master VP and control which + slave goes to which core (more detail shortly). All application code is + animated by slave VPs. When app-code invokes a parallelism construct, + the slave VP first attaches to itself a request representing the + parallelism construct (and destined for the plugin in the master VP) + then suspends. We next review how this request reaches the plugin's + parallelism-construct implementation, called the , + by walking through the steps VMS takes during operation. + + The steps of operation are numbered in + Figure . \ Taking them in order, 1) + scans the scheduling slots to see which ones' + slaves have suspended since the previous scan. \ 2) It hands these to + the request handler plugged-in. \ \ 3) The data in the request causes + the request handler to manipulate data structures within the shared + semantic state. \ These structures hold all the slaves currently + suspended. \ 4) Requests cause slaves to be moved to the ready + container (for the plugin shown, this is one queue on each physical + core -- semantic constructs and work-stealing determine which core a + slave is assigned to). 5) During the scan, the + additionally looks for empty slots. For each, it calls the scheduler + plug-in function, which returns a slave (this plugin just pops the Q). + \ 6) The then places the slave VP's pointer into + the scheduling slot, making it available to the . + \ 7) When done with the scan, suspends, switching + animation back to the . \ 8) + takes slave VPs out of the slots, then 9) switches animation to them. + \ 10) When a slave self-suspends (due to app-code), animation returns + to the , which picks another, until 11) all slots + are empty and the again switches animation to the + . + + <\with|par-first|0fn> + <\with|par-left|0cm> + + + + + Internal elements of VMS + implementation > + + In this + particular implementation we use a central to + ensure that only one core's can be active at any + time. \ This guarantees non-overlap of s on + different cores, allowing the plugins to use sequential algorithms. + + + + + We implemented blocked dense matrix multiply and ran on + a Core2Quad 2.4Ghz chip. + + As shown in Table 1, time to implement + the three parallel libraries averages 2 days. As an example of + productivity, adding nested transactions, parallel singleton, and atomic + function-execution to SSR required a single afternoon, totaling less than + 100 lines of C code. + + |||||||>||||>||||>||||>||||>>>>|Person-days + to design, code, and test each parallelism library, in the order + attempted. L.O.C. is lines of (original) code, excluding libraries and + comments.>>>>>> + + \ Performance of VMS is seen in Table + . The code has not been designed for speed, + but rather to be easy to understand and modify. In particular, the + schedulers are simple queues with no optimization for performance. + + <\with|par-mode|left> + ||||||||||||||>||||>|>|||>||||>||||>||||>||||>||||>||||>||||>||||>||||>||||>||||>||||>>>>|Cycles of + overhead, per scheduled slave. ``comp only'' is perfect memory, ``comp + + mem'' is actual cycles. ``Plugin-concur'' only concurrency requests, + ``plugin-all'' includes create and malloc requests. Two significant + digits due to variability.>>>>>> + + + Comparing our implementation of the + and constructs against the distributed + version of Cilk, the same application code has similar performance. VCilk + does 23% worse on large matrices that run for several seconds, but 210% + better on small matrices requiring only milliseconds. Versus pthreads, + our VMS based implementation has more than an order of magnitude better + overhead per invocation of mutex or condition variable functionality. + + Conclusion> + + This is a position paper, merely a suggestion for a support system for + cooperatively achieving performance portability. The key pattern is the + funneling of many applications to the same parallelism information at the + top, the funneling of many hardware platforms to the same abstraction at + the bottom, and the set of plugins that connect the two ends. + + + <\bibliography|bib|Helpers/plain|Helpers/Bib_for_papers.bib> + <\bib-list|10> + DKU-ized Deblocking Filter code. + http://dku.svn.sourceforge.net/viewvc/dku/branches/DKU_C__Deblocking__orig/. + + Anant Agarwal. Limits on + interconnection network performance. + , 2:398 -- 412, 1991. + + G.Agha, I.Mason, + S.Smith, and C.Talcott. A foundation for actor + computation. , 7(01):1--72, 1997. + + K.Aida, A.Takefusa, + H.Nakada, S.Matsuoka, S.Sekiguchi, and + U.Nagashima. Performance evaluation model for + scheduling in global computing systems. + , 14:268--279, 2000. + + Jason Ansel, CyChan, + YeeLok Wong, Marek Olszewski, Qin Zhao, Alan Edelman, and Saman + Amarasinghe. Petabricks: a language and compiler for + algorithmic choice. In , PLDI '09, pages 38--49, 2009. + + Cédric Augonnet, Samuel Thibault, + Raymond Namyst, and Pierre-André Wacrenier. StarPU: A + unified platform for task scheduling on heterogeneous multicore + architectures. In , Lecture Notes in Computer Science, pages + 863--874. 2009. + + B.Catanzaro, S.Kamil, + Y.Lee, K.Asanovic, J.Demmel, K.Keutzer, + J.Shalf, K.Yelick, and A.Fox. Sejits: + Getting productivity and performance with selective embedded jit + specialization. , 2009. + + Charles Consel. A general + approach for run-time specialization and its application to c. + pages 145--156. ACM Press, 1996. + + Intel Corp. TBB home page. + http://www.threadingbuildingblocks.org. + + Sebastien Donadio, James Brodman, + Thomas Roeder, Kamen Yotov, Denis Barthou, Albert Cohen, María + Garzarán, David Padua, and Keshav Pingali. A language for + the compact representation of multiple program versions. In + , Lecture Notes in Computer Science, pages 136--151. 2006. + + EDuesterwald. + Design and engineering of a dynamic binary optimizer. + , 93:436 -- + 448, 2005. + + Kayvon Fatahalian, DanielReiter + Horn, TimothyJ. Knight, Larkhoon Leem, Mike Houston, + JiYoung Park, Mattan Erez, Manman Ren, Alex Aiken, + WilliamJ. Dally, and Pat Hanrahan. Sequoia: programming + the memory hierarchy. In , + page83, 2006. + + Grigori Fursin, Albert Cohen, Michael + O’Boyle, and Olivier Temam. A practical method for quickly + evaluating program optimizations. In Tom Conte, Nacho + Navarro, Wen-mei Hwu, Mateo Valero, and Theo Ungerer, editors, + , Lecture Notes in Computer Science, pages 29--46. Springer + Berlin / Heidelberg, 2005. + + Jörn Gehring and Friedhelm Ramme. + Architecture-independent request-scheduling with tight + waiting-time estimations. In , volume 1162 of + , pages + 65--88. 1996. + + D.Gelernter. + Generative communication in Linda. + , 7(1):80--112, 1985. + + Jia Guo, Ganesh Bikshandi, + BasilioB. Fraguela, MariaJ. Garzaran, and David Padua. + Programming with tiles. In + , PPoPP '08, pages + 111--122, 2008. + + Sean Halle. VMS home page. + http://vmsexemodel.sourceforge.net. + + Sean Halle and Albert Cohen. + An extensible virtualization mechanism to replace threads. + submitted to PLDI 2011. + + Sean Halle and Albert Cohen. + Dku pattern for performance portable parallel software, 2009. + http://www.soe.ucsc.edu/share/technical-reports/2009/ucsc-soe-09-06.pdf. + + Sean Halle and Albert Cohen. + Leveraging semantics attached to function calls to isolate + applications from hardware. In , June 2010. + + Carl Hewitt. Actor model of + computation, 2010. http://arxiv.org/abs/1008.1459. + + C.A.R. Hoare. + Communicating sequential processes. + , + 21(8):666--677, 1978. + + GLeavens and + MSitaraman (eds). . Cambridge University Press, + 2000. + + Robin Milner. + . Cambridge University Press, 1999. + + OpenMP organization. + OpenMP home page. http://www.openmp.org. + + M.Rosenblum and + T.Garfinkel. Virtual machine monitors: current + technology and future trends. , 38:39 -- 47, 2005. + + Ajeet Shankar, S.Subramanya + Sastry, Rastislav Bodík, and JamesE. Smith. Runtime + specialization with optimistic heap analysis. In + , OOPSLA '05, pages 327--343, 2005. + + Xiaolan Zhang, Zheng Wang, Nicholas + Gloy, J.Bradley Chen, and MichaelD. Smith. System + support for automatic profiling and optimization. In + , SOSP '97, pages 15--26, 1997. + + + + \; + + \; + + +<\initial> + <\collection> + + + + + + + + + + + + + + +<\references> + <\collection> + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + > + + + +<\auxiliary> + <\collection> + <\associate|bib> + PetaBricks09 + + BLISInHotPar + + DKUTechRep + + Sejits + + Shankar05 + + Rosenblum05 + + Sequoia06 + + VMSSubmitted + + VMSHome + + Hewitt10 + + Actors97 + + ComponentModel00 + + hoare78 + + milner99 + + Gelernter85Linda + + TBBHome + + OpenMPHome + + Fursin05 + + Consel96 + + Duesterwald05 + + Zhang97 + + Agarwal91 + + Aida00 + + Augonnet09 + + DKUTechRep + + DeblockingCode + + Padua08 + + Donadio06 + + Gehring96 + + <\associate|figure> + > + + <\tuple|normal> + \; + + The toolchain is split into parallel and sequential portions. The + parallel portion generates the bodies of information-carrying + functions that the plugin later calls to retrieve the info. + > + + > + + Internal elements of VMS + implementation |> + + <\associate|table> + Person-days to design, code, and + test each parallelism library, in the order attempted. L.O.C. is lines + of (original) code, excluding libraries and + comments.|> + + Cycles of overhead, per + scheduled slave. ``comp only'' is perfect memory, ``comp + mem'' is + actual cycles. ``Plugin-concur'' only concurrency requests, + ``plugin-all'' includes create and malloc requests. Two significant + digits due to variability.|> + + <\associate|toc> + |math-font-series||1Overview + and Motivation> |.>>>>|> + + + |math-font-series||2Overview + of VMS> |.>>>>|> + + + |math-font-series||3Specialization> + |.>>>>|> + + + |3.1Three-step specialization + |.>>>>|> + > + + |Isolating parallelism in the toolchain: + |.>>>>|> + > + + |Focus Area: + |.>>>>|> + > + + |What task information to extract: + |.>>>>|> + > + + |Info exposed by VMS to plugin: + |.>>>>|> + > + + |Focus Area: + |.>>>>|> + > + + |math-font-series||4Eco-System> + |.>>>>|> + + + |math-font-series||5Internal + Workings of VMS> |.>>>>|> + + + |Steps of Operation: + |.>>>>|> + > + + |Sequential implementation of parallel + constructs: |.>>>>|> + > + + |math-font-series||6VMS + Measurements> |.>>>>|> + + + |Setup: |.>>>>|> + > + + |Implementation-Time: + |.>>>>|> + > + + |Execution Performance: + |.>>>>|> + > + + |Head to Head: + |.>>>>|> + > + + |math-font-series||7Conclusion> + |.>>>>|> + + + |math-font-series||Bibliography> + |.>>>>|> + + + + \ No newline at end of file diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/PStack/Eco_System/Latex/HotPar_template.la --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/PStack/Eco_System/Latex/HotPar_template.la Sun Apr 08 09:00:10 2012 -0700 @@ -0,0 +1,219 @@ +% TEMPLATE for Usenix papers, specifically to meet requirements of +% USENIX '05 +% originally a template for producing IEEE-format articles using LaTeX. +% written by Matthew Ward, CS Department, Worcester Polytechnic Institute. +% adapted by David Beazley for his excellent SWIG paper in Proceedings, +% Tcl 96 +% turned into a smartass generic template by De Clarke, with thanks to +% both the above pioneers +% use at your own risk. Complaints to /dev/null. +% make it two column with no page numbering, default is 10 point + +% Munged by Fred Douglis 10/97 to separate +% the .sty file from the LaTeX source template, so that people can +% more easily include the .sty file into an existing document. Also +% changed to more closely follow the style guidelines as represented +% by the Word sample file. + +% Note that since 2010, USENIX does not require endnotes. If you want +% foot of page notes, don't include the endnotes package in the +% usepackage command, below. + +% This version uses the latex2e styles, not the very ancient 2.09 stuff. +\documentclass[letterpaper,twocolumn,10pt]{article} +\usepackage{usenix,epsfig,endnotes} +\begin{document} + +%don't want date printed +\date{} + +%make title bold and 14 pt font (Latex default is non-bold, 16 pt) +\title{\Large \bf Wonderful : A Terrific Application and Fascinating Paper} + +%for single author (just remove % characters) +\author{ +{\rm Your N.\ Here}\\ +Your Institution +\and +{\rm Second Name}\\ +Second Institution +% copy the following lines to add more authors +% \and +% {\rm Name}\\ +%Name Institution +} % end author + +\maketitle + +% Use the following at camera-ready time to suppress page numbers. +% Comment it out when you first submit the paper for review. +\thispagestyle{empty} + + +\subsection*{Abstract} +Your Abstract Text Goes Here. Just a few facts. +Whet our appetites. + +\section{Introduction} + +A paragraph of text goes here. Lots of text. Plenty of interesting +text. \\ + +More fascinating text. Features\endnote{Remember to use endnotes, not footnotes!} galore, plethora of promises.\\ + +\section{This is Another Section} + +Some embedded literal typset code might +look like the following : + +{\tt \small +\begin{verbatim} +int wrap_fact(ClientData clientData, + Tcl_Interp *interp, + int argc, char *argv[]) { + int result; + int arg0; + if (argc != 2) { + interp->result = "wrong # args"; + return TCL_ERROR; + } + arg0 = atoi(argv[1]); + result = fact(arg0); + sprintf(interp->result,"%d",result); + return TCL_OK; +} +\end{verbatim} +} + +Now we're going to cite somebody. Watch for the cite tag. +Here it comes~\cite{Chaum1981,Diffie1976}. The tilde character (\~{}) +in the source means a non-breaking space. This way, your reference will +always be attached to the word that preceded it, instead of going to the +next line. + +\section{This Section has SubSections} +\subsection{First SubSection} + +Here's a typical figure reference. The figure is centered at the +top of the column. It's scaled. It's explicitly placed. You'll +have to tweak the numbers to get what you want.\\ + +% you can also use the wonderful epsfig package... +\begin{figure}[t] +\begin{center} +\begin{picture}(300,150)(0,200) +\put(-15,-30){\special{psfile = fig1.ps hscale = 50 vscale = 50}} +\end{picture}\\ +\end{center} +\caption{Wonderful Flowchart} +\end{figure} + +This text came after the figure, so we'll casually refer to Figure 1 +as we go on our merry way. + +\subsection{New Subsection} + +It can get tricky typesetting Tcl and C code in LaTeX because they share +a lot of mystical feelings about certain magic characters. You +will have to do a lot of escaping to typeset curly braces and percent +signs, for example, like this: +``The {\tt \%module} directive +sets the name of the initialization function. This is optional, but is +recommended if building a Tcl 7.5 module. +Everything inside the {\tt \%\{, \%\}} +block is copied directly into the output. allowing the inclusion of +header files and additional C code." \\ + +Sometimes you want to really call attention to a piece of text. You +can center it in the column like this: +\begin{center} +{\tt \_1008e614\_Vector\_p} +\end{center} +and people will really notice it.\\ + +\noindent +The noindent at the start of this paragraph makes it clear that it's +a continuation of the preceding text, not a new para in its own right. + + +Now this is an ingenious way to get a forced space. +{\tt Real~$*$} and {\tt double~$*$} are equivalent. + +Now here is another way to call attention to a line of code, but instead +of centering it, we noindent and bold it.\\ + +\noindent +{\bf \tt size\_t : fread ptr size nobj stream } \\ + +And here we have made an indented para like a definition tag (dt) +in HTML. You don't need a surrounding list macro pair. +\begin{itemize} +\item[] {\tt fread} reads from {\tt stream} into the array {\tt ptr} at +most {\tt nobj} objects of size {\tt size}. {\tt fread} returns +the number of objects read. +\end{itemize} +This concludes the definitions tag. + +\subsection{How to Build Your Paper} + +You have to run {\tt latex} once to prepare your references for +munging. Then run {\tt bibtex} to build your bibliography metadata. +Then run {\tt latex} twice to ensure all references have been resolved. +If your source file is called {\tt usenixTemplate.tex} and your {\tt + bibtex} file is called {\tt usenixTemplate.bib}, here's what you do: +{\tt \small +\begin{verbatim} +latex usenixTemplate +bibtex usenixTemplate +latex usenixTemplate +latex usenixTemplate +\end{verbatim} +} + + +\subsection{Last SubSection} + +Well, it's getting boring isn't it. This is the last subsection +before we wrap it up. + +\section{Acknowledgments} + +A polite author always includes acknowledgments. Thank everyone, +especially those who funded the work. + +\section{Availability} + +It's great when this section says that MyWonderfulApp is free software, +available via anonymous FTP from + +\begin{center} +{\tt ftp.site.dom/pub/myname/Wonderful}\\ +\end{center} + +Also, it's even greater when you can write that information is also +available on the Wonderful homepage at + +\begin{center} +{\tt http://www.site.dom/\~{}myname/SWIG} +\end{center} + +Now we get serious and fill in those references. Remember you will +have to run latex twice on the document in order to resolve those +cite tags you met earlier. This is where they get resolved. +We've preserved some real ones in addition to the template-speak. +After the bibliography you are DONE. + +{\footnotesize \bibliographystyle{acm} +\bibliography{../common/bibliography}} + + +\theendnotes + +\end{document} + + + + + + + diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/PStack/Eco_System/Latex/Tips on Producing PDF Files from LaTeX.pdf Binary file 0__Papers/PStack/Eco_System/Latex/Tips on Producing PDF Files from LaTeX.pdf has changed diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/PStack/Eco_System/Latex/USENIX Consent Form for Refereed Papers.pdf Binary file 0__Papers/PStack/Eco_System/Latex/USENIX Consent Form for Refereed Papers.pdf has changed diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/PStack/Eco_System/Latex/usenix.sty --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/PStack/Eco_System/Latex/usenix.sty Sun Apr 08 09:00:10 2012 -0700 @@ -0,0 +1,94 @@ +% usenix.sty - to be used with latex2e for USENIX. +% To use this style file, look at the template usenix_template.tex +% +% $Id: usenix.sty,v 1.2 2005/02/16 22:30:47 maniatis Exp $ +% +% The following definitions are modifications of standard article.sty +% definitions, arranged to do a better job of matching the USENIX +% guidelines. +% It will automatically select two-column mode and the Times-Roman +% font. + +% +% USENIX papers are two-column. +% Times-Roman font is nice if you can get it (requires NFSS, +% which is in latex2e. + +\if@twocolumn\else\input twocolumn.sty\fi +\usepackage{mathptmx} % times roman, including math (where possible) + +% +% USENIX wants margins of: 1" sides, 1" bottom, and 1" top. +% 0.25" gutter between columns. +% Gives active areas of 6.5" x 9" +% +\setlength{\textheight}{9.0in} +\setlength{\columnsep}{0.25in} +\setlength{\textwidth}{6.50in} + +\setlength{\topmargin}{0.0in} + +\setlength{\headheight}{0.0in} + +\setlength{\headsep}{0.0in} + +% Usenix wants no page numbers for camera-ready papers, so that they can +% number them themselves. But submitted papers should have page numbers +% for the reviewers' convenience. +% +% +% \pagestyle{empty} + +% +% Usenix titles are in 14-point bold type, with no date, and with no +% change in the empty page headers. The whole author section is 12 point +% italic--- you must use {\rm } around the actual author names to get +% them in roman. +% +\def\maketitle{\par + \begingroup + \renewcommand\thefootnote{\fnsymbol{footnote}}% + \def\@makefnmark{\hbox to\z@{$\m@th^{\@thefnmark}$\hss}}% + \long\def\@makefntext##1{\parindent 1em\noindent + \hbox to1.8em{\hss$\m@th^{\@thefnmark}$}##1}% + \if@twocolumn + \twocolumn[\@maketitle]% + \else \newpage + \global\@topnum\z@ + \@maketitle \fi\@thanks + \endgroup + \setcounter{footnote}{0}% + \let\maketitle\relax + \let\@maketitle\relax + \gdef\@thanks{}\gdef\@author{}\gdef\@title{}\let\thanks\relax} + +\def\@maketitle{\newpage + \vbox to 2.5in{ + \vspace*{\fill} + \vskip 2em + \begin{center}% + {\Large\bf \@title \par}% + \vskip 0.375in minus 0.300in + {\large\it + \lineskip .5em + \begin{tabular}[t]{c}\@author + \end{tabular}\par}% + \end{center}% + \par + \vspace*{\fill} +% \vskip 1.5em + } +} + +% +% The abstract is preceded by a 12-pt bold centered heading +\def\abstract{\begin{center}% +{\large\bf \abstractname\vspace{-.5em}\vspace{\z@}}% +\end{center}} +\def\endabstract{} + +% +% Main section titles are 12-pt bold. Others can be same or smaller. +% +\def\section{\@startsection {section}{1}{\z@}{-3.5ex plus-1ex minus + -.2ex}{2.3ex plus.2ex}{\reset@font\large\bf}} diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/PStack/Eco_System/Latex/usenixTemplate.bib --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/PStack/Eco_System/Latex/usenixTemplate.bib Sun Apr 08 09:00:10 2012 -0700 @@ -0,0 +1,23 @@ +@article{Chaum1981, + author = {David L. Chaum}, + title = {{Untraceable electronic mail, return addresses, and + digital pseudonyms}}, + journal = {Communications of the {ACM}}, + volume = {24}, + number = {2}, + year = {1981}, + pages = {84--90}, + publisher = {ACM Press}, +} + +@article{Diffie1976, + author = "Whitfield Diffie and Martin E. Hellman", + title = {{New Directions in Cryptography}}, + journal = "IEEE Transactions on Information Theory", + volume = "IT-22", + number = "6", + pages = "644--654", + month = nov, + year = "1976" +} + diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/PStack/Eco_System/USENIX Consent Form for Refereed Papers.pdf Binary file 0__Papers/PStack/Eco_System/USENIX Consent Form for Refereed Papers.pdf has changed diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/PStack/Eco_System/consent_pg_1.pdf Binary file 0__Papers/PStack/Eco_System/consent_pg_1.pdf has changed diff -r fdd66fbc9403 -r 254d86cf269d 0__Papers/PStack/Eco_System/consent_pg_1.svg --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/0__Papers/PStack/Eco_System/consent_pg_1.svg Sun Apr 08 09:00:10 2012 -0700 @@ -0,0 +1,338 @@ + + + +image/svg+xmlSupport of Collective Effort Towards Performance Portability +CONSENT FORM for REFEREED PAPERSHotPar '11: 3rd USENIX Workshop on Hot Topics in ParallelismMay 26–27, 2011, Berkeley, CA, USA +We must receive your signed consent form at the time you submit your files. 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