1.1 --- a/0__Papers/Holistic_Model/Perf_Tune/latex/Holistic_Perf_Tuning.tex	Fri May 04 05:23:17 2012 -0700
     1.2 +++ b/0__Papers/Holistic_Model/Perf_Tune/latex/Holistic_Perf_Tuning.tex	Fri May 04 05:26:00 2012 -0700
     1.3 @@ -180,7 +180,7 @@
     1.4  
     1.5  
     1.6  % *** SUBFIGURE PACKAGES ***
     1.7 -%\usepackage[tight,footnotesize]{subfigure}
     1.8 +%\usepackage[tight,footnotesize]{subfig}
     1.9  % subfigure.sty was written by Steven Douglas Cochran. This package makes it
    1.10  % easy to put subfigures in your figures. e.g., "Figure 1a and 1b". For IEEE
    1.11  % work, it is a good idea to load it with the tight package option to reduce
    1.12 @@ -283,7 +283,9 @@
    1.13  
    1.14  
    1.15  
    1.16 -\title{Performance Tuning Requires Integrating Aspects of Application, Runtime, Scheduling, and Hardware..  OR Integrated Performance Tuning Using Semantic Information Collected by Instrumenting the Language Runtime}
    1.17 +\title{Performance Tuning Requires Integrating Aspects of Application, Runtime, Scheduling, and Hardware..\\
    1.18 +OR Performance Tuning Requires Connecting Application to Runtime, Scheduling, and Hardware\\
    1.19 +  OR Integrated Performance Tuning Using Semantic Information Collected by Instrumenting the Language Runtime}
    1.20  
    1.21  \author{
    1.22          Nina Engelhardt\\
    1.23 @@ -326,10 +328,13 @@
    1.24  The views connect the units to specific segments of code that compose the units, and connect each constraint on scheduling choice to the precise source of the constraint, within the code, hardware, or runtime. They should also separate resource usage into categories of: application work, non-overlapped communication (which results from scheduling decisions), and scheduling/runtime overhead. They should also integrate parameter choices within the code that affect unit creation and constraints.
    1.25  
    1.26  =====
    1.27 + 
    1.28   The value of a consequence graph is linking the size of boxes in it to the decisions made by the scheduler, which are represented by the shape. This lets a person visually link scheduling decisions to consequences.  The mind can quickly see empty areas, representing lost performance, and connect those to boxes and lines that cause the empty areas.  They then look up the code of each box and construct of each line, which gives them the code structures that caused the loss of performance.  This \emph{visual} linkage of undesirable effect back to \emph{cause in the code} is what sets our approach apart. 
    1.29  The value of the UCC is visually linking cause of performance loss to options available for fixing it.
    1.30 +
    1.31  =====  
    1.32  
    1.33 +
    1.34  We introduce in this paper a model of computation that ties all aspects of performance together, along with instrumentation and visualization that is guided by the model and that links all relevant performance tuning information together. The model and visualization tools are illustrated with a story line, which shows how they are used to performance tune a standard parallel application on two multi-core systems. 
    1.35  
    1.36  
    1.37 @@ -604,56 +609,6 @@
    1.38  %\end{figure*}
    1.39  
    1.40  
    1.41 -\section{Setup}
    1.42 -
    1.43 -Preview of what will see in setup
    1.44 -
    1.45 -
    1.46 -\subsection{a bit about development environment and the machines}
    1.47 -
    1.48 -\subsection{SSR Language}
    1.49 -Intro to SSR and its features. 
    1.50 -
    1.51 -\subsection{A bit about the code}
    1.52 -Pics illustrate matrix mult divider code. 
    1.53 -
    1.54 -Pics illustrate processors created and communication between them.
    1.55 -
    1.56 -\subsection{} 
    1.57 -  elements of Holistic Model without explanation: UCC and consequence graph elements.  How consequence graph ties back to features in UCC and to specific segments of code.
    1.58 -
    1.59 -
    1.60 -<a line about lang features support this perf tuning model -- can still do with pthreads, but less effective because don't have clean units nor semantics of constraints on units -- SSR provides these, as do languages like CnC, StarSs, and so on>
    1.61 - 
    1.62 -\subsection{summary of instrumenting language and VMS}
    1.63 -Make point that no application instrumentation -- everything is inside language runtime (part in plugin, part in VMS -- VMS is just a helper to simplify runtime creation).
    1.64 -
    1.65 -Pic from VMS paper, with arrows pointing to places instrumentation injected.
    1.66 -
    1.67 -
    1.68 -\section{The Visualizations}
    1.69 -
    1.70 -<note: use language that talks about the visualizations as seen, but avoid using word "tool" in connection with visualization.. no need to draw attention to fact that we don't have a GUI, the contribution is not a tool, but rather a methodology, and the visualizations are just one element of the methodology>
    1.71 -
    1.72 -show example UCC and consequence graph pictures. 
    1.73 - 
    1.74 -Talk about features of the two graphs, point out how features indicate performance loss, link picture elements that indicate perf loss to sources of loss -- could be param choices, like how many pieces to make, or input choices like size of matrix, or code choices, like how to perform division, or scheduling choices, like how to assign work-units to cores.
    1.75 -
    1.76 -State will see all of these in practice during the story lines of using the visualizations.
    1.77 -
    1.78 -
    1.79 -\section{Illustrative Story of Performance Tuning}
    1.80 -
    1.81 -Overview of steps in story, and what each step will show
    1.82 -
    1.83 -\subsection{Performance Tuning on 1 socket by 4-core Machine}
    1.84 -
    1.85 -Starting point: just wrote code and ran it -- show UCC and consqG pics..  point out glaring visual feature that says a big perf loss..  show how links to cause.. and so on..
    1.86 -
    1.87 -
    1.88 -\subsection{Performance Tuning on 4 socket by 10 core by 2 context Machine}
    1.89 -
    1.90 -Same as for 4 core machine..  this time, point out what choices are different between 40 core and 4 core.
    1.91  
    1.92  \section{The Model Behind the Visualization}
    1.93  
    1.94 @@ -683,19 +638,51 @@
    1.95  
    1.96  
    1.97  \subsection{Scheduling Consequence Graph}
    1.98 -The second part of the model adds-in constraints caused by runtime implementation details and hardware. It then integrates all three aspects of parallel performance: application, runtime, and hardware. The resulting graph identifies all sources of lost performance, and links them to the cause of the loss, as was seen during the tuning story in Section X.
    1.99 +Whereas the UCC concentrates on application-derived information, the second part of the model adds-in constraints caused by runtime implementation details and hardware. It's called the Scheduling Consequence Graph, because it links scheduling decisions to their performance consequences and the hardware details involved with those consequences.
   1.100  
   1.101 +The consequence graph integrates all three aspects of parallel performance: application, runtime, and hardware. It identifies all instances of lost performance, and links them to the cause of the loss, as was seen during the tuning story in Section X.
   1.102 +
   1.103 +This graph captures the three kinds of causal relationships that affect core usage: scheduling decisions invoked by the runtime, dependencies inside the runtime itself, and hardware constraints. Each of these causalities causes some portion of the core usage that took place, and shows up as a feature on the consequence graph. 
   1.104 +
   1.105 +To distinguish from the UCC, the consequence graph shows the behavior resulting from scheduling decisions actually \emph{made},   not which were \emph{possible.} The UCC shows the possibilities. Hence, a consequence graph shows one of the possible sets of choices allowed by the UCC.
   1.106 +
   1.107 +We will now look at each source of causal relationship.
   1.108 +
   1.109 +\paragraph{Scheduling decision causality} Notice that the performance varies between choice-sets. The main reason for the variation is the communication patterns resulting from the particular choices. For a fixed concrete UCC, each set of scheduling choices it allows has a consequent pattern of core usages, which \emph{is} the performance realized. 
   1.110 +
   1.111 +The consequence graph also shows control dependencies from the base language, which may add superfluous constraints that further eliminate some otherwise allowed choices in the UCC. An example would be a \texttt{for} loop that creates work-units -- no parallelism constructs cause a sequentialization of the creations, but the base C language sequentializes it nonetheless. 
   1.112 +
   1.113 +\paragraph{Runtime causal dependencies} are introduced by implementation details. For example, the version of VMS we instrumented to take measurements for this paper relies upon a global lock for shared semantic-constraint information. This lock introduces a causal dependency that only allows the runtime to execute on one core at any horizontal line in the consequence graph.
   1.114 +
   1.115 + Normally, these are not displayed explicitly, due to clutter, but can be turned on when needed, say, to figure out the cause of a particular pattern of core usage.
   1.116 +
   1.117 +\paragraph{Hardware causal dependencies} are due to the physical fact that a given resource can only be used by one work-unit at a time. A (logical) core only executes one work-unit at a time. A communication link is occupied by one packet at a time, and so on. 
   1.118 +
   1.119 +These are also not normally displayed, due to clutter, and not all hardware dependencies are directly measured. Future work will focus on using the performance counters and other instrumentation to add more information about communication paths taken as a consequence of the scheduling decisions made. This takes the current linkage of application-code to runtime decisions, and adds consequent communication patterns, which are the primary free variable in resulting performance. This gives an end-to-end linkage between code choices and caused behavior on the hardware for performance. 
   1.120 +
   1.121 +Three sources of causality: application-derived, runtime, and hardware. 
   1.122 +
   1.123 +How consequence graph features each tie back to features in UCC and to specific segments of code or constructs.
   1.124 +
   1.125 +In detail, the consequence graph
   1.126 +\subsubsection{A precise definition of Consequence Graph} A consequence graph accounts for each bit of core time. It has boxes that each represent one segment of core time, and arcs between the boxes that each represent a causal dependency between boxes. Each box is counted as associated to one work-unit, and then all boxes counted to the same unit are collected into a node.
   1.127 +
   1.128 +There are several kinds of boxes, one for each reason that the core is being used (or being forced idle), and several kinds of arcs, one for each type of causal dependency.
   1.129 +
   1.130 +The box types are arranged by cause of core usage: application work, waiting for communication of work data, runtime internals, managing constraints, and choosing assignment of work onto cores. The runtime internals have sub-categories but space is limited so we skip those here.
   1.131 +
   1.132 +The arc types are arranged by source of the causal relationship: base-language control dependencies, parallel semantic constraint which fed into a particular choice in the runtime (IE, the choice ties together two specific work-units so the one completing causes other to start), runtime internal causality such as a global lock or a distributed quorum algorithm which creates causal dependencies between boxes that represent execution of internal runtime code, and arcs that represent hardware causal relationships, such as one work-unit finishing on a core causes another work-unit to start there, given the choice by the runtime. This should give a reasonably precise description of the arcs, while the finer details are beyond the scope of this paper.
   1.133  
   1.134  \subsection{Levels of UCC and Consequence Graph}
   1.135 -There is one last twist to the story of UCCs and consequence graphs, which is that there are levels of them, which correspond to the levels of scheduler in a hierarchical machine. We use an example involving a server machine with a hierarchy of runtimes to illustrate both, concentrating first on just the UCC then adding the consequence graph. 
   1.136 +There is one last twist to the story of UCCs and consequence graphs, which is that there are levels of them that correspond to the levels of scheduler in a hierarchical machine. We use an example involving a server machine with a hierarchy of runtimes to illustrate both, concentrating first on just the UCCs, then adding the consequence graph. 
   1.137  
   1.138  \subsubsection{Levels of UCC}
   1.139  
   1.140 -As the example, consider  a server with one rack,  having a back-plane that boards plug into. A board has its own memory with four sockets, each having a chip with four cores. So there is a back-plane network connecting the boards,  a bus on each board that connects the sockets to the DRAM, and inside the chip in each socket is a cache hierarchy that connects the cores.
   1.141 +For the example, consider  a server with one rack,  having a back-plane that boards plug into. A board has its own memory with four sockets, each having a chip with four cores. So there is a back-plane network connecting the boards,  a bus on each board that connects the sockets to the DRAM, and inside the chip in each socket is a cache hierarchy that connects the cores.
   1.142  
   1.143  The hardware is given a set of runtimes to match the hierarchy. Each network or bus has a runtime that schedules work onto the things connected below it. So the top runtime divides work among the boards, while each board has a runtime that divides work among the sockets, and each socket has a runtime that divides work among the cores.  
   1.144  
   1.145 -To a runtime high up, each runtime below it looks like a complete machine. It schedules work-units to these machines, without knowing the internal details of how that machine is implemented. So the runtime at the top handles very large work-units that it schedules onto the boards. The runtime on a board, meanwhile, divides up the work it gets into smaller work-units, and schedules one onto each socket, and so on.
   1.146 +To a runtime high up, each runtime below it looks like a complete machine. It schedules work-units to these machines, without knowing the internal details of how that machine is implemented. So the runtime at the top handles very large work-units that it schedules onto the boards. The runtime on a board, meanwhile, divides up the work-unit it gets into smaller work-units, and schedules one onto each socket, and so on.
   1.147  
   1.148  The application in this example has been written in a language that allows work to be divided. The toolchain inserted a manipulator that allows each runtime to divide up the work it is given into smaller work-units. This pushed the UCC of the application all the way to the right on the unit axis.  
   1.149  
   1.150 @@ -709,164 +696,94 @@
   1.151  
   1.152  A consequence graph ties together scheduling decisions made on units with the consequences in the hardware of those decisions. The goal is to charge each segment of time on a physical core to exactly one box in a consequence graph.
   1.153  
   1.154 -In the UCCs, for a higher up runtime, each lower runtime it schedules onto is treated as a machine. We saw in Fig X that a unit has its own UCC in the level below it, so there is a corresponding consequence graph. The UCC states the degrees of scheduling freedom, while the consequence graph shows the hardware consequences resulting from the particular scheduling choices made in the runtime.
   1.155 +In the UCCs, for a higher up runtime, each lower runtime it schedules onto is treated as a machine. We saw in Fig X that a unit has and entire  UCC in the level below, so there is a corresponding consequence graph. The UCC states the degrees of scheduling freedom, while the consequence graph shows the hardware consequences resulting from the particular scheduling choices made in the runtime.
   1.156  
   1.157 - Now, the question is, what hardware usage should get counted towards one of the units? The answer is: only the time spent on the cores that is used to schedule, do work, and wait for non-overlapped communication.
   1.158 + Now, the question is, what hardware usage should get counted towards one of the units? The answer is: only the time spent on the cores that is used to schedule, do work, and wait for non-overlapped communication of that unit.
   1.159  
   1.160  The time spent on scheduling one of the units is straight-forward, it's the normal runtime overhead of receiving a unit, managing the constraints on it, and choosing the best location and time to execute it.  The only variation is that the location chosen is a lower-level runtime rather than a physical core.
   1.161  
   1.162 -But what core time should be charged as the work of that unit? The answer is: the core time not accounted for in the descendent consequence graphs. Each segement of physical core time can only be charged to one box in one consequence graph, so only the leaf graphs count the actual work. Further, the time spent in the lower runtime spent receiving, handling constraints, and choosing when and where to schedule the sub-units is charged to boxes in the lower-level consequence graph.  By the process of elimination, the only time not accounted for elsewhere is the time spent dividing up a unit into smaller ones, and time spent accumulating the individual results back together. So this is what gets charged to the work-time box for a unit.
   1.163 +But what core time should be charged as the work of that unit? The answer is: the core time not accounted for in the descendent consequence graphs. Each segment of physical core time can only be charged to one box in one consequence graph, so only the leaf graphs count the actual work. Further, the time spent in the lower runtime spent receiving, handling constraints, and choosing when and where to schedule the sub-units is charged to boxes in the lower-level consequence graph.  By the process of elimination, the only time not accounted for elsewhere is the time spent dividing up a unit into smaller ones, and time spent accumulating the individual results back together. So this is what gets charged to the work-time box for a unit.
   1.164  
   1.165 -The last question is how to handle communication consequences. This is tricky because decisions in higher-level runtimes set the context for decisions in lower-level ones. This means a higher-level choice is linked to the consequences from lower-level choices. The value of a consequence graph is linking the size of boxes in it to the decisions made by the scheduler as represented by the shape. It's not clear how to divide among the levels the time that cores spend waiting for non-overlapped communication. We have no good answer at the moment and leave it for future work.
   1.166 +The last question is how to handle communication consequences. This is tricky because decisions in higher-level runtimes set the context for decisions in lower-level ones. This means a higher-level choice is linked to the consequences from lower-level choices. The value of a consequence graph is linking the size of boxes in it to the decisions made by the scheduler, as represented by the shape. It's not clear how to divide, among the levels, the time that cores spend waiting for non-overlapped communication. We have no good answer at the moment and leave it for future work.
   1.167 +
   1.168 +\section{Conclusion}
   1.169 +We have shown how to apply a computation model to instrument a language runtime for collecting measurements that connect: to each other, to application structure, to scheduling decisions, and to hardware. A simple visualization of the data has features that indicate lost performance, and features that visually link the lost performance to the cause, no matter if the cause is application structure, language runtime implementation, or hardware feature.  It is this linkage, due to the computation model, that sets this approach apart from others. 
   1.170 + 
   1.171 +
   1.172 +\bibliography{BibForPapers}
   1.173 + 
   1.174 +\end{document}
   1.175 +
   1.176 +======
   1.177 +
   1.178 +Check-list -- be sure catch these:
   1.179 +
   1.180 +Pic illustrates matrix mult divider algorithm. 
   1.181 +
   1.182 +Pic illustrate processors created and communication between them.
   1.183 +
   1.184 +How consequence graph features each tie back to features in UCC and to specific segments of code or constructs.
   1.185 +
   1.186 +
   1.187 +Which lang features support model -- units, plus clear constraints on them -- can still do with pthreads, but less effective because don't have clean units nor semantics of constraints on units -- SSR provides these, as do languages like CnC, StarSs, and so on
   1.188 + 
   1.189 +No application instrumentation -- everything is inside language runtime (part in plugin, part in VMS -- VMS is just a helper to simplify runtime creation).
   1.190 +
   1.191 +Pic from VMS paper, with arrows pointing to places instrumentation injected.
   1.192 +
   1.193 +Avoid word "tool" in connection with visualization.. no need to draw attention to fact that we don't have a GUI, the contribution is not a tool, but rather a methodology, and the visualizations are just one element of the methodology
   1.194 +
   1.195 +Semantic information from application-code: The units, constraints on them, type of constraint, code executed in unit
   1.196 +
   1.197 +visual link perf-loss to code, as cause (or perf-loss to runtime or HW)
   1.198 +
   1.199 +visual: units, sched decision on each, hardware assigned to, runtime overhead on each, constraints bounded choice of hardware and order
   1.200 +
   1.201 +constraints color-coded by language-defined type
   1.202 +
   1.203 +visually, performance issue is pattern of either idle time or overhead
   1.204 +Together: visual links to units involved in perf-loss, which links to code-snippet, and to parallelism-construct defining the unit boundary and the construct constraining its scheduling.
   1.205 +
   1.206 +collect info by instrumenting runtime of lang -- do once, works all apps
   1.207 +
   1.208 +ties visual features to app-code segments -- despite app-independent
   1.209 +
   1.210 +Benefit: simple see perf-loss features, simple to link to cause in code, straight-forward to devise a fix.
   1.211 +
   1.212 +visual show unit linked to overhead in runtime to handle the constraints on unit, and choose its assignment to HW.
   1.213 +
   1.214 +Visual: idle of core from comm, NOT comm itself -- Rather than indicate how much time a communication takes, the visualization instead indicates how much idle time is caused on a core as a consequence of that communication.  This is the most useful-to-observe cost, of the communication. It naturally accounts for overlap, and only alerts the person tuning when there is a true cost, when the core idles.
   1.215 +
   1.216 +visual: non-ov comm + work, accounts cache-misses on out-of-order.  The second aspect of communication is the emergent effect of cache misses on computation rate.  As such, the relative size of work-units is visualized, which includes the cost of cache misses, given a shared-memory multi-core machine.
   1.217 +
   1.218 +three prevalent classes of performance loss are clearly displayed by our visualization: runtime overhead (including lock acquisition time), communication cost (both cache misses and runtime internal control communications), and poor scheduling choices (assign work in an order that causes idle time on cores)
   1.219 +
   1.220 +VMS == easy instrument lang -- Properties of VMS make it easy to instrument other languages, so the technique is straight-forward to apply to any VMS-based language.  For UCC, have to make own data struct for lang-specific dependencies.  For units, can be generic and pulled down into VMS.  VMS provides support for the instrumentation -- describe standard things support. Reuse code btwn plugins, for units, and common communication constructs (?)
   1.221  
   1.222   
   1.223 -\end{document}
   1.224 +UCC is application-derived degrees of freedom for picking assignment of work to HW resources.
   1.225 +
   1.226 +N to N construct -- ex of not-dependency but still constraint
   1.227 +
   1.228 +how features indicate performance loss, and link picture elements that indicate perf loss to sources of loss -- could be param choices, like how many pieces to make, or input choices like size of matrix, or code choices, like how to perform division, or scheduling choices, like how to assign work-units to cores.
   1.229 +
   1.230 +show UCC and consqG pics..  point out glaring visual feature that says a big perf loss..  show how links to cause.. and so on..
   1.231  
   1.232  ==============================
   1.233  
   1.234  \section{Random Early Thoughts}
   1.235  
   1.236 -The units are semantic information, the constraints on them are semantic information, the type of constraint is semantic information.  The code executed inside a unit is semantic information.
   1.237 -
   1.238 -UCC shows application-defined constraints on units -- these are the degrees of freedom for picking assignment of work to HW resources.
   1.239 -
   1.240 -When tuning performance, these types of semantic information work together -- they make it easy to spot performance issues (idle time or runtime overhead), and then link information about the code to the issue.  A visualization shows the scheduled units of work, the hardware those units are assigned to, the runtime overhead counted towards each unit, and the constraints that bounded the choice of which hardware and which order to assign the units.  Further, the constraints are color-coded by language-defined type of constraint. Hence, a performance issue appears as a pattern of either idle time or overhead, and the visualization links the units involved, as seen in the visualization, directly to the code-snippet of the unit, and the parallelism-construct that the unit.
   1.241 -
   1.242 -In this paper, we present an approach for collecting this information by instrumenting the runtime of a language that is based on VMS.  The instrumentation is done once for the language, then reused across applications.  Despite being independent of application, it ties specific features in the visualization to specific segments of code, to make it easy to spot performance problems, simple to understand what in the code is causing the problem, and straight-forward to devise a fix for the problem.
   1.243 -
   1.244 -The visualization identifies each unit of work that is scheduled by the runtime, and indicates how much overhead was spent in the runtime to handle the constraints and choose an assignment.
   1.245 -
   1.246 -Rather than indicate how much time a communication takes, the visualization instead indicates how much idle time is caused on a core as a consequence of that communication.  This is the most useful-to-observe cost, of the communication. It naturally accounts for overlap, and only alerts the person tuning when there is a true cost, when the core idles.
   1.247 -
   1.248 -The second aspect of communication is the emergent effect of cache misses on computation rate.  As such, the relative size of work-units is visualized, which includes the cost of cache misses, given a shared-memory multi-core machine.
   1.249 -
   1.250 -Hence, the three prevalent classes of performance loss are clearly displayed by our visualization: runtime overhead (including lock acquisition time), 
   1.251 -
   1.252 -
   1.253 -
   1.254 -Properties of VMS make it easy to instrument other languages, so the technique is straight-forward to apply to any VMS-based language.  For UCC, have to make own data struct for lang-specific dependencies.  For units, can be generic and pulled down into VMS.  VMS provides support for the instrumentation -- describe standard things support.
   1.255 -
   1.256 -Copy-pastable code: identifying units, common communication constructs
   1.257 -
   1.258 -Non-copyable: weird comm-construct (N to N), have to save dependencies correspond to that.
   1.259  
   1.260  Key places in plugin code for instrumentation -- places in the request handler that change state of a VP -- track down in plugin code every place that VP state changes, and put instrumentation there.
   1.261  
   1.262  If have a mutex -- is an acquire and a release -- VP only interacts with sem env, not another VP, but dependencies are between VPs, so have to record the sequence of interactions with semantic environment to establish causality chain (even though it's a runtime causilty chain, not necessarily an app constraint)
   1.263 +
   1.264  For Vthread, no UCC, only consequence graph.
   1.265  
   1.266 -
   1.267 -\subsection{Subsection}
   1.268 -
   1.269 -Text for the first sub-section.
   1.270 -
   1.271 -
   1.272 -\subsection{Subsection}
   1.273 -
   1.274 -Text for the second sub-section.
   1.275 -
   1.276 -\subsubsection{Subsubsection}
   1.277 -Text for the first sub-sub-section.
   1.278 -
   1.279 -\subsubsection{Subsubsection}
   1.280 -Text for the second sub-sub-section.
   1.281 -
   1.282 -
   1.283 -\subsection{Subsection}
   1.284 -
   1.285 -Text for the third sub-section.
   1.286 -
   1.287 -
   1.288 -
   1.289 -\section{Section}
   1.290 -
   1.291 -Text for the second section.
   1.292 -
   1.293 -
   1.294 -
   1.295 -\section{Figures and Tables}
   1.296 -
   1.297 -Text for the third section. This section has figures and tables in it.
   1.298 -
   1.299 -\begin{figure}
   1.300 -\centering
   1.301 -\fbox{figure matter}
   1.302 -\caption{This is the caption for figure \#1. Make sure it goes
   1.303 -        \emph{after} the figure!}
   1.304 -\label{figure1}
   1.305 -\end{figure}
   1.306 -
   1.307 -And more text in this section.
   1.308 -
   1.309 -\begin{table}
   1.310 -\caption{This is the caption for table \#1. Make sure it goes
   1.311 -\emph{before} the table!}
   1.312 -\label{table1}
   1.313 -\centering
   1.314 -table matter
   1.315 -\end{table}
   1.316 -
   1.317 -Figure and table references: \figref{figure1}, \tabref{table1}. Use
   1.318 -these at the beginning and within a sentence.
   1.319 -
   1.320 -Much better is to use the Figure and Table environments, which will
   1.321 -take care of placing the caption correctly for you. See
   1.322 -\fref{figurelabel} and \tref{tablelabel}.
   1.323 -
   1.324 -Using the Figure environment:
   1.325 -\begin{Figure}[h]{figurelabel}% <- don't forget this percent!
   1.326 -        {Caption for figure, Figure environment.}
   1.327 -\fbox{The figure matter goes here.}
   1.328 -\end{Figure}
   1.329 -
   1.330 -text
   1.331 -
   1.332 -Using the Table environment:
   1.333 -\begin{Table}{tablelabel}% <- don't forget this percent!
   1.334 -        {Caption for table, Table environment.}
   1.335 -\fbox{The table matter goes here.}
   1.336 -\end{Table}
   1.337 -
   1.338 -And more text in this section.
   1.339 -And more text in this section.
   1.340 -And more text in this section.
   1.341 -And more text in this section.
   1.342 -And more text in this section.
   1.343 -
   1.344 -
   1.345 -
   1.346 -\section{Equations}
   1.347 -
   1.348 -Referencing equations: \equref{equation1} for whatever.
   1.349 -\Equref{equation1} at the beginning of a sentence. 
   1.350 -%
   1.351 -\begin{equation}
   1.352 -equation
   1.353 -\label{equation1}
   1.354 -\end{equation}
   1.355 -%
   1.356 -text
   1.357 -
   1.358 -
   1.359 -
   1.360 -\bibliography{FilenameOfYourBibliography}
   1.361 -
   1.362 -
   1.363 -
   1.364 -\section{Test of Biographies}
   1.365 -
   1.366 -text
   1.367 -
   1.368 -\begin{biography}{Author 1}[0mm]{file.eps}
   1.369 -
   1.370 -\end{biography}
   1.371 -
   1.372 -
   1.373 -\end{document}
   1.374 -
   1.375 -?
   1.376 +Can apply this model to pthreads, but UCC has no useful info because units of work are not well defined -- they are instead defined in the application code -- application normally implementes an application-specific runtime as part of app -- mutexes and cond variables force adding application-related work-unit semantics to the application, in effect creating an application-specific language, via implementing an application-specific runtime.  That semantic information is not available to the pthreads language, and so is not capturable in a pthreads derived UCC. -- picture illustrates runtime, which embodies language construct semantics -- how SSR has two levels, but pthreads has three..
   1.377  
   1.378  =============
   1.379 +What's broken in others:
   1.380  
   1.381   the   or have cache misses over time, but never have a coherent view of how application code connects to what happens where and when. 
   1.382  
   1.383 @@ -875,20 +792,35 @@
   1.384  The problem of the other vis is they don't give shape of application..
   1.385   the fundamental parallelism related structure.
   1.386  
   1.387 -===================
   1.388 -
   1.389 -
   1.390 -
   1.391 -as well as which choices on them are allowed, and which were actually taken. Finally, 
   1.392 -
   1.393 -the application-imposed constraints on scheduling them, the hardware-imposed constraints on scheduling them, and the runtime-implementation imposed constraints on scheduling them. 
   1.394 -
   1.395 - Scheduling is a fundamental part of parallel execution. The views must include both constraints on scheduling and the actual scheduling choices. The parts that affect what scheduling choices are possible must connect to the parts that show which ones were taken.
   1.396  
   1.397  to have more theoretical underpinning and several views that connect to each other. The user needs more information, with some mental framework to 
   1.398  
   1.399  a lot of the time it's lists of measurements, or bar graphs, things like that -- over the whole application or by function -- forcing guessing of how it connects to -- if it tells you that this line creates a lot of level 2 cache misses, that doesn't tell you what the application is doing to cause this.. but when have whole UCC along with it, have context for the measurements -- puts the line of code into a framework -- it's necessary but not useful by itself -- it needs to be connected -- the unit information is more interesting than the line of code information -- line of code has only sequential meaning, missing scheduling connection -- need the scheduling behavior added -- need to know the unit of work that's causing problem, not the line of code -- unit provides a parallelism context, line of code does not.. unit provides an execution order and execution location, with implied communication -- line of code does not.
   1.400  
   1.401 +===================
   1.402 +
   1.403 +Perf bounded by: the application-imposed constraints on scheduling units, the hardware-imposed constraints on scheduling them, and the runtime-implementation imposed constraints on scheduling them. 
   1.404 +
   1.405 +
   1.406 +Par Comp Model:  Scheduling is a fundamental part of parallel execution. The views must include both constraints on scheduling and the actual scheduling choices. The parts that affect what scheduling choices are possible must connect to the parts that show which ones were taken.
   1.407 +
   1.408 +
   1.409 +==========  Table ref, figure environment, table environment
   1.410 + \tabref{table1}.
   1.411 + 
   1.412 +Using the Figure environment:
   1.413 +\begin{Figure}[h]{figurelabel}% <- don't forget this percent!
   1.414 +        {Caption for figure, Figure environment.}
   1.415 +\fbox{The figure matter goes here.}
   1.416 +\end{Figure}
   1.417 +
   1.418 +Table environment:
   1.419 +\begin{Table}{tablelabel}% <- don't forget this percent!
   1.420 +        {Caption for table, Table environment.}
   1.421 +\fbox{The table matter goes here.}
   1.422 +\end{Table}
   1.423 +
   1.424 +
   1.425  %%
   1.426  %% EOF ieeepes_skel.tex
   1.427  %%----------------------------------------------------------------------

     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
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     2.3 @@ -0,0 +1,916 @@
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   2.118 +}
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   2.124 +}
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   2.133 +}
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   2.151 +	numpages = 8
   2.152 +}
   2.153 +@TechReport{Halle_GainFromChaos_TechRep,
   2.154 +	author = {Halle, K.S. and Chua, Leon O. and Anishchenko, V.S. and Safonova, M.A.},
   2.155 +	title = {Signal Amplification via Chaos: Experimental Evidence},
   2.156 +	institution = {EECS Department, University of California, Berkeley},
   2.157 +	year = 1992,
   2.158 +	url = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1992/2223.html},
   2.159 +	number = {UCB/ERL M92/130}
   2.160 +}
   2.161 +@Article{Halle_GainFromChaos_pub,
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   2.163 +	title = {Signal Amplification via Chaos: Experimental Evidence},
   2.164 +	journal = {Int. J. of Bifurcation and Chaos },
   2.165 +	pages = {290-308},
   2.166 +	year = 1993
   2.167 +}
   2.168 +@Article{Halle_SpreadSpect_pub,
   2.169 +	author = {K.S. Halle and C.W. Wu and M. Itoh and L. O. Chua},
   2.170 +	title = {Spread Spectrum Communication Through Modulation of Chaos},
   2.171 +	journal = {Int. J. of Bifurcation and Chaos },
   2.172 +	pages = {469-477},
   2.173 +	year = 1993,
   2.174 +	note = {cited by 232}
   2.175 +}
   2.176 +@Article{Halle_Secure_pub,
   2.177 +	author = {V. Kocarev and K.S. Halle and K. Eckert and L. O. Chua and V. Parlitz},
   2.178 +	title = {Experimental Demonstration of Secure Communications Via Chaotic Synchronization},
   2.179 +	journal = {Int. J. of Bifurcation and Chaos },
   2.180 +	pages = {709-713},
   2.181 +	year = 1992,
   2.182 +	note = {cited by 457}
   2.183 +}
   2.184 +@InProceedings{HotPar10_w_BLIS,
   2.185 +	author = {Sean Halle and Albert Cohen},
   2.186 +	booktitle = {HOTPAR '10: USENIX Workshop on Hot Topics in Parallelism},
   2.187 +	month = {June},
   2.188 +	title = {Leveraging Semantics Attached to Function Calls to Isolate Applications from Hardware},
   2.189 +	year = 2010
   2.190 +}
   2.191 +@InProceedings{HotPar11_w_Stack,
   2.192 +	author = {Sean Halle and Albert Cohen},
   2.193 +	booktitle = {HOTPAR '11: USENIX Workshop on Hot Topics in Parallelism},
   2.194 +	month = {May},
   2.195 +	title = {Support of Collective Effort Towards Performance Portability},
   2.196 +	year = 2011
   2.197 +}
   2.198 +@Article{VMS_LCPC_11,
   2.199 +	author = {Sean Halle and Albert Cohen},
   2.200 +	title = {A Mutable Hardware Abstraction to Replace Threads},
   2.201 +	journal = {24th International Workshop on Languages and Compilers for Parallel Languages (LCPC11)},
   2.202 +	year = 2011
   2.203 +}
   2.204 +@Misc{StackTechRep_10,
   2.205 +	author = {Halle, Sean and Nadezhkin, Dmitry and Cohen, Albert},
   2.206 +	note = {http://www.soe.ucsc.edu/share/technical-reports/2010/ucsc-soe-10-02.pdf},
   2.207 +	title = {A Framework to Support Research on Portable High Performance Parallelism},
   2.208 +	year = 2010
   2.209 +}
   2.210 +@Misc{CTBigStepSemTechRep_06,
   2.211 +	author = {Halle, Sean},
   2.212 +	note = {http://www.soe.ucsc.edu/share/technical-reports/2006/ucsc-crl-06-11.pdf},
   2.213 +	title = {The Big-Step Operational Semantics of CodeTime Circuits},
   2.214 +	year = 2006
   2.215 +}
   2.216 +@Misc{MentalFrameworkTechRep_06,
   2.217 +	author = {Halle, Sean},
   2.218 +	note = {http://www.soe.ucsc.edu/share/technical-reports/2006/ucsc-crl-06-12.pdf},
   2.219 +	title = {A Mental Framework for use in Creating Hardware Independent Parallel Languages},
   2.220 +	year = 2006
   2.221 +}
   2.222 +@Misc{DKUTechRep_09,
   2.223 +	author = {Halle, Sean and Cohen, Albert},
   2.224 +	note = {http://www.soe.ucsc.edu/share/technical-reports/2009/ucsc-soe-09-06.pdf},
   2.225 +	title = {DKU Pattern for Performance Portable Parallel Software},
   2.226 +	year = 2009
   2.227 +}
   2.228 +@Misc{EQNLangTechRep,
   2.229 +	author = {Halle, Sean},
   2.230 +	note = {http://www.soe.ucsc.edu/share/technical-reports/2009/ucsc-soe-09-16.pdf},
   2.231 +	title = {An Extensible Parallel Language},
   2.232 +	year = 2009
   2.233 +}
   2.234 +@Misc{CTOSTechRep,
   2.235 +	author = {Halle, Sean},
   2.236 +	note = {http://www.soe.ucsc.edu/share/technical-reports/2009/ucsc-soe-09-15.pdf},
   2.237 +	title = {A Hardware-Independent Parallel Operating System Abstraction Layer for Parallelism},
   2.238 +	year = 2009
   2.239 +}
   2.240 +@Misc{SideEffectsTechRep,
   2.241 +	author = {Halle, Sean and Cohen, Albert},
   2.242 +	note = {http://www.soe.ucsc.edu/share/technical-reports/2009/ucsc-soe-09-14.pdf},
   2.243 +	title = {Parallel Language Extensions for Side Effects},
   2.244 +	year = 2009
   2.245 +}
   2.246 +@Misc{BaCTiLTechRep,
   2.247 +	author = {Halle, Sean},
   2.248 +	note = {http://www.soe.ucsc.edu/share/technical-reports/2006/ucsc-crl-06-08.pdf},
   2.249 +	title = {BaCTiL: Base CodeTime Language},
   2.250 +	year = 2006
   2.251 +}
   2.252 +@Misc{CTPlatformTechRep,
   2.253 +	author = {Halle, Sean},
   2.254 +	note = {http://www.soe.ucsc.edu/share/technical-reports/2006/ucsc-crl-06-09.pdf},
   2.255 +	title = {The Elements of the CodeTime Software Platform},
   2.256 +	year = 2006
   2.257 +}
   2.258 +@Misc{CTRTTechRep,
   2.259 +	author = {Halle, Sean},
   2.260 +	note = {http://www.soe.ucsc.edu/share/technical-reports/2006/ucsc-crl-06-10.pdf},
   2.261 +	title = {A Scalable and Efficient Peer-to-Peer Run-Time System for a Hardware Independent Software Platform},
   2.262 +	year = 2006
   2.263 +}
   2.264 +@Misc{CIPTechRep,
   2.265 +	author = {Halle, Sean},
   2.266 +	note = {http://www.soe.ucsc.edu/share/technical-reports/2005/ucsc-crl-05-05.pdf},
   2.267 +	title = {The Case for an Integrated Software Platform for {HEC} Illustrated Using the CodeTime Platform},
   2.268 +	year = 2005
   2.269 +}
   2.270 +@Misc{DKU_Infra_site,
   2.271 +	author = {Sean Halle and Albert Cohen},
   2.272 +	note = {http://omp.musictwodotoh.com},
   2.273 +	title = {{DKU} infrastructure server}
   2.274 +}
   2.275 +@Misc{DKUSourceForge,
   2.276 +	author = {Sean Halle and Albert Cohen},
   2.277 +	month = {November},
   2.278 +	note = {http://dku.sourceforge.net},
   2.279 +	title = {{DKU} website},
   2.280 +	year = 2008
   2.281 +}
   2.282 +@Misc{BLISHome,
   2.283 +	author = {Sean Halle and Albert Cohen},
   2.284 +	month = {November},
   2.285 +	note = {http://blisplatform.sourceforge.net},
   2.286 +	title = {{BLIS} website},
   2.287 +	year = 2008
   2.288 +}
   2.289 +@Misc{VMSHome,
   2.290 +	author = {Sean Halle and Merten Sach and Ben Juurlink and Albert Cohen},
   2.291 +	note = {http://virtualizedmasterslave.org},
   2.292 +	title = {{VMS} Home Page},
   2.293 +	year = 2010
   2.294 +}
   2.295 +@Misc{PStackHome,
   2.296 +	author = {Sean Halle},
   2.297 +	note = {http://pstack.sourceforge.net},
   2.298 +	title = {{PStack} Home Page -- A Software Stack for Performantly Portable Parallelism},
   2.299 +	year = 2012
   2.300 +}
   2.301 +@Misc{DeblockingCode,
   2.302 +	note = {http://dku.svn.sourceforge.net/viewvc/dku/branches/DKU\_C\_\_Deblocking\_\_orig/},
   2.303 +	title = {{DKU-ized Deblocking Filter} code}
   2.304 +}
   2.305 +@Misc{SampleBLISCode,
   2.306 +	note = {http://dku.sourceforge.net/SampleCode.htm},
   2.307 +	title = {{Sample BLIS Code}}
   2.308 +}
   2.309 +@Misc{OMPHome,
   2.310 +	note = {http://www.openmediaplatform.eu/},
   2.311 +	title = {{Open Media Platform} homepage}
   2.312 +}
   2.313 +@Misc{MapReduceHome,
   2.314 +	author = {Google Corp.},
   2.315 +	note = {http://labs.google.com/papers/mapreduce.html},
   2.316 +	title = {{MapReduce} Home page}
   2.317 +}
   2.318 +@Misc{TBBHome,
   2.319 +	author = {Intel Corp.},
   2.320 +	note = {http://www.threadingbuildingblocks.org},
   2.321 +	title = {{TBB} Home page}
   2.322 +}
   2.323 +@Misc{HPFWikipedia,
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   2.325 +	note = {http://en.wikipedia.org/wiki/High_Performance_Fortran},
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   2.327 +}
   2.328 +@Misc{OpenMPHome,
   2.329 +	author = {{OpenMP} organization},
   2.330 +	note = {http://www.openmp.org},
   2.331 +	title = {{OpenMP} Home page}
   2.332 +}
   2.333 +@Misc{MPIHome,
   2.334 +	author = {open-mpi organization},
   2.335 +	note = {http://www.open-mpi.org},
   2.336 +	title = {{Open MPI} Home page}
   2.337 +}
   2.338 +@Misc{OpenCLHome,
   2.339 +	author = {Kronos Group},
   2.340 +	note = {http://www.khronos.org/opencl},
   2.341 +	title = {{OpenCL} Home page}
   2.342 +}
   2.343 +@Misc{CILKHome,
   2.344 +	author = {Cilk group at MIT},
   2.345 +	note = {http://supertech.csail.mit.edu/cilk/},
   2.346 +	title = {{CILK} homepage}
   2.347 +}
   2.348 +@InProceedings{Fri98,
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   2.353 +	year = 1998,
   2.354 +	address = {Montreal, Quebec},
   2.355 +	month = jun
   2.356 +}
   2.357 +@Misc{TitaniumHome,
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   2.359 +	title = {{Titanium} homepage}
   2.360 +}
   2.361 +@InProceedings{CnCInHotPar,
   2.362 +	author = {Knobe, Kathleen},
   2.363 +	booktitle = {HOTPAR '09: USENIX Workshop on Hot Topics in Parallelism},
   2.364 +	title = {Ease of Use with Concurrent Collections {(CnC)}},
   2.365 +	year = 2009
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   2.818 +	publisher = {Cambridge University Press},
   2.819 +	year = 1999
   2.820 +}
   2.821 +@Book{MPIForum94,
   2.822 +	author = {M. P. I. Forum},
   2.823 +	title = {MPI: A Message-Passing Interface Standard},
   2.824 +	year = 1994
   2.825 +}
   2.826 +@Article{petri62,
   2.827 +	title = {{Fundamentals of a theory of asynchronous information flow}},
   2.828 +	author = {Petri, C.A.},
   2.829 +	journal = {Proc. IFIP Congress},
   2.830 +	volume = 62,
   2.831 +	pages = {386--390},
   2.832 +	year = 1962
   2.833 +}
   2.834 +@Book{pierce02,
   2.835 +	title = {Types and Programming Languages},
   2.836 +	author = {Pierce, B. C.},
   2.837 +	year = 2002,
   2.838 +	publisher = {MIT Press}
   2.839 +}
   2.840 +@Article{price,
   2.841 +	author = {B. A. Price and R. M. Baecker and L. S. Small},
   2.842 +	title = {A Principled Taxonomy of Software Visualization},
   2.843 +	journal = {Journal of Visual Languages and Computing},
   2.844 +	volume = 4,
   2.845 +	number = 3,
   2.846 +	pages = {211--266}
   2.847 +}
   2.848 +@Misc{pythonWebSite,
   2.849 +	key = {Python},
   2.850 +	title = {The Python Software Foundation Mission Statement},
   2.851 +	note = {{\ttfamily http://www.python.org/psf/mission.html}}
   2.852 +}
   2.853 +@Unpublished{reed03,
   2.854 +	editor = {Daniel A. Reed},
   2.855 +	title = {Workshop on The Roadmap for the Revitalization of High-End Computing},
   2.856 +	day = {16--18},
   2.857 +	month = {jun},
   2.858 +	year = 2003,
   2.859 +	note = {Available at {\ttfamily http://www.cra.org/reports/supercomputing.web.pdf}}
   2.860 +}
   2.861 +@Article{reeves84,
   2.862 +	author = {A. P. Reeves},
   2.863 +	title = {Parallel Pascal -- An Extended Pascal for Parallel Computers},
   2.864 +	journal = {Journal of Parallel and Distributed Computing},
   2.865 +	volume = 1,
   2.866 +	number = {},
   2.867 +	year = 1984,
   2.868 +	month = {aug},
   2.869 +	pages = {64--80}
   2.870 +}
   2.871 +@Article{skillicorn98,
   2.872 +	author = {David B. Skillicorn and Domenico Talia},
   2.873 +	title = {Models and languages for parallel computation},
   2.874 +	journal = {ACM Comput. Surv.},
   2.875 +	volume = 30,
   2.876 +	number = 2,
   2.877 +	year = 1998,
   2.878 +	issn = {0360-0300},
   2.879 +	pages = {123--169},
   2.880 +	doi = {http://doi.acm.org/10.1145/280277.280278},
   2.881 +	publisher = {ACM Press},
   2.882 +	address = {New York, NY, USA}
   2.883 +}
   2.884 +@Article{stefik86,
   2.885 +	title = {Object Oriented Programming: Themes and Variations},
   2.886 +	author = {Stefik, M. and Bobrow, D. G.},
   2.887 +	journal = {The AI Magazine},
   2.888 +	volume = 6,
   2.889 +	number = 4,
   2.890 +	year = 1986
   2.891 +}
   2.892 +@Book{stirling92,
   2.893 +	title = {{Modal and Temporal Logics}},
   2.894 +	author = {Stirling, C.},
   2.895 +	year = 1992,
   2.896 +	publisher = {University of Edinburgh, Department of Computer Science}
   2.897 +}
   2.898 +@Misc{TitaniumWebSite,
   2.899 +	author = {Paul Hilfinger and et. al.},
   2.900 +	title = {The Titanium Project Home Page},
   2.901 +	note = {{\ttfamily http://www.cs.berkeley.edu/projects/titanium}}
   2.902 +}
   2.903 +@Misc{turing38,
   2.904 +	author = {A. Turing},
   2.905 +	note = {http://www.turingarchive.org/intro/, and http://www.turing.org.uk/sources/biblio4.html, and http://web.comlab.ox.ac.uk/oucl/research/areas/ieg/e-library/sources/tp2-ie.pdf},
   2.906 +	year = 1938
   2.907 +}
   2.908 +@Book{vonNeumann45,
   2.909 +	title = {First Draft of a Report on the EDVAC},
   2.910 +	author = {J. von Neumann},
   2.911 +	year = 1945,
   2.912 +	publisher = {United States Army Ordnance Department}
   2.913 +}
   2.914 +@Book{winskel93,
   2.915 +	title = {{The Formal Semantics of Programming Languages}},
   2.916 +	author = {Winskel, G.},
   2.917 +	year = 1993,
   2.918 +	publisher = {MIT Press}
   2.919 +}

     3.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.2 +++ b/CVs/12_Ap__Euro_Fellowship_CV/euro_fellowship_CV.tex	Fri May 04 05:26:00 2012 -0700
     3.3 @@ -0,0 +1,170 @@
     3.4 +%&latex
     3.5 +%% Derived from: `cvctan.tex'
     3.6 +
     3.7 +\documentclass[a4paper]{article}
     3.8 +
     3.9 +\usepackage{tabularx}
    3.10 +
    3.11 +%\usepackage{doublespace}
    3.12 +%\setstretch{1.1}
    3.13 +
    3.14 +%\usepackage{ae}
    3.15 +\usepackage[T1]{fontenc}
    3.16 +\usepackage{CV}
    3.17 +
    3.18 +
    3.19 +\oddsidemargin 0in
    3.20 +\evensidemargin 0in
    3.21 +\textwidth\paperwidth
    3.22 +\advance \textwidth by -2in
    3.23 +\topmargin 0in
    3.24 +\textheight\paperheight
    3.25 +\advance\textheight -2in
    3.26 +\headheight 0pt
    3.27 +\headsep 0pt
    3.28 +\footskip 0pt
    3.29 +
    3.30 +
    3.31 +%%%%%%%%%%%%%%%%%%%%%%
    3.32 +\begin{document}
    3.33 +
    3.34 +\pagestyle{empty}
    3.35 +
    3.36 +%Ueberschrift
    3.37 +\begin{center}
    3.38 +\huge{\textsc{Curriculum Vitae}}
    3.39 +\vspace{\baselineskip}
    3.40 +
    3.41 +\Large{\textsc{Sean Halle}}
    3.42 +\end{center}
    3.43 +%\vspace{1.5\baselineskip}
    3.44 +
    3.45 +\section{}
    3.46 +\noindent\hspace*{\tabcolsep}
    3.47 +\begin{minipage}{0.4\linewidth}
    3.48 +
    3.49 +{\large{\textsc{Address}}}\\
    3.50 +17 Einsteinufer Rm 647 \\
    3.51 +10587 Berlin\\[3pt]
    3.52 +Tel~: +49~30~314~73130\\
    3.53 +EMail~: \texttt{sean.halle@tu-berlin.de}
    3.54 +\end{minipage}
    3.55 +\begin{minipage}{0.4\linewidth}
    3.56 +
    3.57 +{\large{\textsc{Personal Details}}}\\
    3.58 +Nationality: US\\
    3.59 +Gender: Male\\
    3.60 +\\
    3.61 +
    3.62 +\end{minipage}
    3.63 +
    3.64 +\section{Overview/Summary} Sean is a researcher and sometimes entrepreneur.  As an undergraduate and masters student, his research at UC Berkeley demonstrated the first evidence of secure communication using chaos, spread spectrum communication using a chaotic carrier signal, and gain from perturbation of chaotic circuits, with a total of 450+ citations to these papers.  He left with his Masters in 1994, to pursue starting a company with technology developed during a graduate course, eventually founding a fabless chip company around a MIMD-SIMD low-power massively parallel processor for graphics (ProSide), in 1997.  After the company's demise, he switched to software and worked his way up the chain, ending at Chief Software Architect at Nevik in 2000.  The dot-com crash precipitated a return to academia to start his PhD in 2003, where he worked on parallelism, developing a theory of parallel computation, and a performance-portable software stack. As part of this, in 2008 he was invited by Albert Cohen to work in Paris at INRIA, the national computer science research institute for France, concentrating on new parallel languages for high productivity and high performance portability.  This led to BLIS and VMS, two technologies that became the basis of his dissertation, for which he received his PhD in 2011.  He is currently a post-doctorate researcher at TU Berlin, focusing on processor architecture to support portable parallelism, and a software stack to support performance-portable parallel languages.
    3.65 +
    3.66 +
    3.67 +
    3.68 +\section{Education}
    3.69 +
    3.70 +\begin{CV}
    3.71 +\item[May 1992:] UC Berkeley, BSEE, Dept. of Electrical Engineering and Computer Science.
    3.72 +\item[May 1994:] UC Berkeley, MSEE,  Dept. of Electrical Engineering and Computer Science.
    3.73 +
    3.74 +Thesis on \emph{Experimental Chaos}.  Published the first papers in the field on "Gain from Chaos," "Spread Spectrum Communication Using Chaos," and "Secure Communication Using Chaos." The papers, combined, have garnered in excess of 450 citations. Advisor: Leon O Chua.
    3.75 +
    3.76 +\item[June 2011:] UC Santa Cruz, PhD,  Dept. of Computer Engineering.
    3.77 +
    3.78 +Dissertation on \emph{theory of parallel computation and tools for delivering performance-portable parallel software}. Advisors: Albert Cohen (INRIA, Paris), and Jose Renau (UC Santa Cruz).
    3.79 +
    3.80 +\end{CV}
    3.81 +
    3.82 +
    3.83 +\section{Experience}
    3.84 +
    3.85 +\begin{CV}
    3.86 +
    3.87 +\item[Jun '11 to Jun '12:]  Post-doctorate researcher at Technical University Berlin.
    3.88 +
    3.89 + Overseeing 6 students who are working  on: verifying the Holistic Model of Parallel Computation (proposed in Dissertation), design of a low-power GPU that is free from programming and application restrictions, improvement of Virtualized Master-Slave (VMS) (from Dissertation), and implementation of the HWSim language on top of VMS. 
    3.90 +
    3.91 +\item[Apr '08 to Apr '11:]  INRIA, Paris and Ecole Normale Supereur: Performed research on Portable High Performance Parallelism.  
    3.92 +
    3.93 +In 2008-2009 period demonstrated DKU and BLIS framework in Java and in C, running on multi-core shared memory machines, a heterogeneous collection of them and on the Cell processor.  In 2010 and 2011 designed WorkTable language for high productivity parallel coding for Enterprise applications, and HWSim for high-performance simulation of hardware designs, using parallel host machines. In 2011 delivered Virtualized Master-Slave (VMS), a hardware abstraction to simplify creation and implementation of domain-specific parallel languages, and the basis of a software stack for performant-portable parallel software.  The work there formed the main results in his dissertation.
    3.94 +
    3.95 +\item[Sept '03 to Apr '08:] UC Santa Cruz: Performed research on a theory of parallel computation, and developed a programming system for performance-portable software called CodeTime, in addition to an analytic performance model for out-of-order pipelines.
    3.96 +
    3.97 +\item[Apr '02 to Sept '03:]  Freelance: In anticipation of starting a fabless chip company, architected an ultra low power multi-threaded high-throughput processor.  Developed a detailed analytic model of the processor.  Wrote behavioral code and a test suite to demonstrate its performance.  Pursued series-A funding.  
    3.98 +
    3.99 +\item[Dec '00 to Apr '02:] Nevik Networks: As Chief Software Architect, designed and was responsible for the team implementing a telecom abstraction layer that provides web-based end-customer provisioning of big-iron class 5 switches as well as soft-switches.  Led development, drove requirements gathering and scoping of the product.
   3.100 +
   3.101 +\item[Dec '99 to Dec '00:] SRI International:  A member of SRI's enterprise software consulting spin-off.  Designed a high speed trading system for Deutsche Bank's fixed income securities market.  Co-architected, for American Century, an integrated financial system.  Contributed papers analyzing and detailing electronic exchanges.  Technical lead on implementation of a financial planning services exchange.
   3.102 +
   3.103 +\item[Apr '99 to Dec '99:] Cisco Systems, contract:  Member of web based ordering tool team (\$15 Billion in orders annually via this tool).  Added functionality via modifying front-end servlet code, back-end business logic, and Oracle database tables.
   3.104 +
   3.105 +\item[Apr '98 to Mar '99:] Sun Microsystems, JavaSoft division,  contract:   Participated in debug of the AWT portion of the Java language for the 1.2 release.  Contributed to specification of the automated GUI testing API that later appeared in release 1.5.  Developed automated testing tools.
   3.106 +
   3.107 +\item[Mar '96 to Dec '97:] ProSide Inc.  Acquired funding for a novel architecture fusing SIMD and SPMD of his design.  Targeted at 3D graphics, was also a general "loop accelerator" that appeared as smart-memory.  Developed base programming language and tools.
   3.108 +
   3.109 +\item[Jan '95 to Jan '96:] Digital Equipment Corporation:  Held position created for him by Dan Dobberpuhl to evaluate advanced technologies for use in Alpha processors.  Evaluated adiabatic logic, Time-Stationary Computation, and other low power, high speed technologies.  Invented five new logic families and a novel division technique based on deduction.  Designed high speed pseudo-self-timed array multiplier for low cost Alpha core and StrongArm VLIW co-processor using a combination of static, domino, and differential cascode (DCVSL) logic.
   3.110 +
   3.111 +
   3.112 +\end{CV}
   3.113 +
   3.114 +\pagebreak
   3.115 +\section{References}
   3.116 +
   3.117 +\noindent These persons are familiar with my professional qualifications and my character:
   3.118 +
   3.119 +\begin{table}[ht]
   3.120 +\begin{tabular}{@{}lll@{}}
   3.121 +\textbf{Prof. Albert Cohen} \\
   3.122 +Thesis supervisor & Phone: & +33-1-44-32-21-67\\
   3.123 +Department d'Informatiqe & Email & albert.cohen@inria.fr\\
   3.124 +Ecole Normale Superieure \\
   3.125 +45 rue d'Ulm\\
   3.126 +75005 Paris\\
   3.127 +France
   3.128 +\end{tabular}
   3.129 +
   3.130 +\vspace{.15in}
   3.131 +\begin{tabular}{@{}lll@{}}
   3.132 +\textbf{Prof. Jose Renau} \\
   3.133 +Thesis supervisor & Phone: & +1-831-459-1847\\
   3.134 + 1156 High Street MS: SOE2 & Email & renau@soe.ucsc.edu\\
   3.135 +Santa Cruz, CA 95064 \\
   3.136 +USA
   3.137 +\end{tabular}
   3.138 +
   3.139 +
   3.140 +\vspace{.15in}
   3.141 +\begin{tabular}{@{}lll@{}}
   3.142 +\textbf{Prof. Ben Juurlink} \\
   3.143 +Post-doc Advisor & Phone: & +49 30 314 73131\\
   3.144 +Technical University Berlin & Email &  b.juurlink@tu-berlin.de\\
   3.145 +Einsteinufer 17 / Sekr. EN12 \\
   3.146 +10587 Berlin\\
   3.147 +Germany
   3.148 +\end{tabular}
   3.149 +
   3.150 +\end{table}
   3.151 +
   3.152 +\end{document}
   3.153 +
   3.154 +
   3.155 +
   3.156 +
   3.157 +
   3.158 +%Tabellen
   3.159 +\begin{table}[htbp] \centering%
   3.160 +\begin{tabular}{lll}\hline\hline
   3.161 +1 & 2 & 3 \\ \hline
   3.162 +1 & \multicolumn{2}{c}{2} \\
   3.163 +\hline
   3.164 +\end{tabular}
   3.165 +\caption{Titel\label{Tabelle: Label}}
   3.166 +\end{table}
   3.167 +
   3.168 +
   3.169 +
   3.170 +
   3.171 +
   3.172 +
   3.173 +

     4.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.2 +++ b/CVs/12_Ap__Euro_Fellowship_CV/euro_fellowship_CV_w_pubs.tex	Fri May 04 05:26:00 2012 -0700
     4.3 @@ -0,0 +1,194 @@
     4.4 +%&latex
     4.5 +%% Derived from: `cvctan.tex'
     4.6 +
     4.7 +\documentclass[a4paper]{article}
     4.8 +
     4.9 +\usepackage{tabularx}
    4.10 +
    4.11 +%\usepackage{doublespace}
    4.12 +%\setstretch{1.1}
    4.13 +
    4.14 +%\usepackage{ae}
    4.15 +\usepackage[T1]{fontenc}
    4.16 +\usepackage{CV}
    4.17 +
    4.18 +
    4.19 +\oddsidemargin 0in
    4.20 +\evensidemargin 0in
    4.21 +\textwidth\paperwidth
    4.22 +\advance \textwidth by -2in
    4.23 +\topmargin 0in
    4.24 +\textheight\paperheight
    4.25 +\advance\textheight -2in
    4.26 +\headheight 0pt
    4.27 +\headsep 0pt
    4.28 +\footskip 0pt
    4.29 +
    4.30 +
    4.31 +%%%%%%%%%%%%%%%%%%%%%%
    4.32 +\begin{document}
    4.33 +
    4.34 +\pagestyle{empty}
    4.35 +\bibliographystyle{plain}
    4.36 +%Ueberschrift
    4.37 +\begin{center}
    4.38 +\huge{\textsc{Curriculum Vitae}}
    4.39 +\vspace{\baselineskip}
    4.40 +
    4.41 +\Large{\textsc{Sean Halle}}
    4.42 +\end{center}
    4.43 +%\vspace{1.5\baselineskip}
    4.44 +
    4.45 +\section{}
    4.46 +\noindent\hspace*{\tabcolsep}
    4.47 +\begin{minipage}{0.4\linewidth}
    4.48 +
    4.49 +{\large{\textsc{Address}}}\\
    4.50 +17 Einsteinufer Rm 647 \\
    4.51 +10587 Berlin\\[3pt]
    4.52 +Tel~: +49~30~314~73130\\
    4.53 +EMail~: \texttt{sean.halle@tu-berlin.de}
    4.54 +\end{minipage}
    4.55 +\begin{minipage}{0.4\linewidth}
    4.56 +
    4.57 +{\large{\textsc{Personal Details}}}\\
    4.58 +Nationality: US\\
    4.59 +Gender: Male\\
    4.60 +\\
    4.61 +
    4.62 +\end{minipage}
    4.63 +
    4.64 +\section{Overview/Summary} Sean is a researcher and sometimes entrepreneur.  As an undergraduate and masters student, his research at UC Berkeley demonstrated the first evidence of secure communication using chaos, spread spectrum communication using a chaotic carrier signal, and gain from perturbation of chaotic circuits, with a total of 450+ citations to these papers.  He left with his Masters in 1994, to pursue starting a company with technology developed during a graduate course, eventually founding a fabless chip company around a MIMD-SIMD low-power massively parallel processor for graphics (ProSide), in 1997.  After the company's demise, he switched to software and worked his way up the chain, ending at Chief Software Architect at Nevik in 2000.  The dot-com crash precipitated a return to academia to start his PhD in 2003, where he worked on parallelism, developing a theory of parallel computation, and a performance-portable software stack. As part of this, in 2008 he was invited by Albert Cohen to work in Paris at INRIA, the national computer science research institute for France, concentrating on new parallel languages for high productivity and high performance portability.  This led to BLIS and VMS, two technologies that became the basis of his dissertation, for which he received his PhD in 2011.  He is currently a post-doctorate researcher at TU Berlin, focusing on processor architecture to support portable parallelism, and a software stack to support performance-portable parallel languages.
    4.65 +
    4.66 +
    4.67 +
    4.68 +\section{Education}
    4.69 +
    4.70 +\begin{CV}
    4.71 +\item[May 1992:] UC Berkeley, BSEE, Dept. of Electrical Engineering and Computer Science.
    4.72 +\item[May 1994:] UC Berkeley, MSEE,  Dept. of Electrical Engineering and Computer Science.
    4.73 +
    4.74 +Thesis on \emph{Experimental Chaos}.  Published the first papers in the field on "Gain from Chaos," "Spread Spectrum Communication Using Chaos," and "Secure Communication Using Chaos." The papers, combined, have garnered in excess of 450 citations. Advisor: Leon O Chua.
    4.75 +
    4.76 +\item[June 2011:] UC Santa Cruz, PhD,  Dept. of Computer Engineering.
    4.77 +
    4.78 +Dissertation on \emph{theory of parallel computation and tools for delivering performance-portable parallel software}. Advisors: Albert Cohen (INRIA, Paris), and Jose Renau (UC Santa Cruz).
    4.79 +
    4.80 +\end{CV}
    4.81 +
    4.82 +
    4.83 +\section{Experience}
    4.84 +
    4.85 +\begin{CV}
    4.86 +
    4.87 +\item[Jun '11 to Jun '12:]  Post-doctorate researcher at Technical University Berlin.
    4.88 +
    4.89 + Overseeing 6 students who are working  on: verifying the Holistic Model of Parallel Computation (proposed in Dissertation), design of a low-power GPU that is free from programming and application restrictions, improvement of Virtualized Master-Slave (VMS) (from Dissertation), and implementation of the HWSim language on top of VMS. 
    4.90 +
    4.91 +\item[Apr '08 to Apr '11:]  INRIA, Paris and Ecole Normale Supereur: Performed research on Portable High Performance Parallelism.  
    4.92 +
    4.93 +In 2008-2009 period demonstrated DKU and BLIS framework in Java and in C, running on multi-core shared memory machines, a heterogeneous collection of them and on the Cell processor.  In 2010 and 2011 designed WorkTable language for high productivity parallel coding for Enterprise applications, and HWSim for high-performance simulation of hardware designs, using parallel host machines. In 2011 delivered Virtualized Master-Slave (VMS), a hardware abstraction to simplify creation and implementation of domain-specific parallel languages, and the basis of a software stack for performant-portable parallel software.  The work there formed the main results in his dissertation.
    4.94 +
    4.95 +\item[Sept '03 to Apr '08:] UC Santa Cruz: Performed research on a theory of parallel computation, and developed a programming system for performance-portable software called CodeTime, in addition to an analytic performance model for out-of-order pipelines.
    4.96 +
    4.97 +\item[Apr '02 to Sept '03:]  Freelance: In anticipation of starting a fabless chip company, architected an ultra low power multi-threaded high-throughput processor.  Developed a detailed analytic model of the processor.  Wrote behavioral code and a test suite to demonstrate its performance.  Pursued series-A funding.  
    4.98 +
    4.99 +\item[Dec '00 to Apr '02:] Nevik Networks: As Chief Software Architect, designed and was responsible for the team implementing a telecom abstraction layer that provides web-based end-customer provisioning of big-iron class 5 switches as well as soft-switches.  Led development, drove requirements gathering and scoping of the product.
   4.100 +
   4.101 +\item[Dec '99 to Dec '00:] SRI International:  A member of SRI's enterprise software consulting spin-off.  Designed a high speed trading system for Deutsche Bank's fixed income securities market.  Co-architected, for American Century, an integrated financial system.  Contributed papers analyzing and detailing electronic exchanges.  Technical lead on implementation of a financial planning services exchange.
   4.102 +
   4.103 +\item[Apr '99 to Dec '99:] Cisco Systems, contract:  Member of web based ordering tool team (\$15 Billion in orders annually via this tool).  Added functionality via modifying front-end servlet code, back-end business logic, and Oracle database tables.
   4.104 +
   4.105 +\item[Apr '98 to Mar '99:] Sun Microsystems, JavaSoft division,  contract:   Participated in debug of the AWT portion of the Java language for the 1.2 release.  Contributed to specification of the automated GUI testing API that later appeared in release 1.5.  Developed automated testing tools.
   4.106 +
   4.107 +\item[Mar '96 to Dec '97:] ProSide Inc.  Acquired funding for a novel architecture fusing SIMD and SPMD of his design.  Targeted at 3D graphics, was also a general "loop accelerator" that appeared as smart-memory.  Developed base programming language and tools.
   4.108 +
   4.109 +\item[Jan '95 to Jan '96:] Digital Equipment Corporation:  Held position created for him by Dan Dobberpuhl to evaluate advanced technologies for use in Alpha processors.  Evaluated adiabatic logic, Time-Stationary Computation, and other low power, high speed technologies.  Invented five new logic families and a novel division technique based on deduction.  Designed high speed pseudo-self-timed array multiplier for low cost Alpha core and StrongArm VLIW co-processor using a combination of static, domino, and differential cascode (DCVSL) logic.
   4.110 +
   4.111 +
   4.112 +\end{CV}
   4.113 +
   4.114 +\pagebreak
   4.115 +\section{Personal References}
   4.116 +
   4.117 +\noindent These persons are familiar with my professional qualifications and my character:
   4.118 +
   4.119 +\begin{table}[ht]
   4.120 +\begin{tabular}{@{}lll@{}}
   4.121 +\textbf{Prof. Albert Cohen} \\
   4.122 +Thesis supervisor & Phone: & +33-1-44-32-21-67\\
   4.123 +Department d'Informatiqe & Email & albert.cohen@inria.fr\\
   4.124 +Ecole Normale Superieure \\
   4.125 +45 rue d'Ulm\\
   4.126 +75005 Paris\\
   4.127 +France
   4.128 +\end{tabular}
   4.129 +
   4.130 +\vspace{.15in}
   4.131 +\begin{tabular}{@{}lll@{}}
   4.132 +\textbf{Prof. Jose Renau} \\
   4.133 +Thesis supervisor & Phone: & +1-831-459-1847\\
   4.134 + 1156 High Street MS: SOE2 & Email & renau@soe.ucsc.edu\\
   4.135 +Santa Cruz, CA 95064 \\
   4.136 +USA
   4.137 +\end{tabular}
   4.138 +
   4.139 +
   4.140 +\vspace{.15in}
   4.141 +\begin{tabular}{@{}lll@{}}
   4.142 +\textbf{Prof. Ben Juurlink} \\
   4.143 +Post-doc Advisor & Phone: & +49 30 314 73131\\
   4.144 +Technical University Berlin & Email &  b.juurlink@tu-berlin.de\\
   4.145 +Einsteinufer 17 / Sekr. EN12 \\
   4.146 +10587 Berlin\\
   4.147 +Germany
   4.148 +\end{tabular}
   4.149 +
   4.150 +\end{table}
   4.151 +
   4.152 +\cite{BLISHome,
   4.153 +HotPar10_w_BLIS,
   4.154 +HotPar11_w_Stack,
   4.155 +PStackHome,
   4.156 +VMS_LCPC_11,
   4.157 +VMSHome,
   4.158 +WorkTableHome,
   4.159 +BaCTiLTechRep,
   4.160 +CIPTechRep,
   4.161 +CTOSTechRep,
   4.162 +CTPlatformTechRep,
   4.163 +CTRTTechRep,
   4.164 +DKUTechRep_09,
   4.165 +EQNLangTechRep,
   4.166 +GainFromChaos_Halle_92,
   4.167 +MentalFrameworkTechRep_06,
   4.168 +Halle_GainFromChaos_pub,
   4.169 +Halle_Secure_pub,
   4.170 +Halle_SpreadSpect_pub}
   4.171 +
   4.172 +\bibliography{bib_for_papers_apr_2012}
   4.173 +
   4.174 +
   4.175 +
   4.176 +\end{document}
   4.177 +
   4.178 +
   4.179 +
   4.180 +
   4.181 +
   4.182 +%Tabellen
   4.183 +\begin{table}[htbp] \centering%
   4.184 +\begin{tabular}{lll}\hline\hline
   4.185 +1 & 2 & 3 \\ \hline
   4.186 +1 & \multicolumn{2}{c}{2} \\
   4.187 +\hline
   4.188 +\end{tabular}
   4.189 +\caption{Titel\label{Tabelle: Label}}
   4.190 +\end{table}
   4.191 +
   4.192 +
   4.193 +
   4.194 +
   4.195 +
   4.196 +
   4.197 +

     5.1 Binary file CVs/12_Ap__Euro_Fellowship_CV/publication_list.pdf has changed

     6.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.2 +++ b/CVs/12_Ap__Euro_Fellowship_CV/publication_list.tex	Fri May 04 05:26:00 2012 -0700
     6.3 @@ -0,0 +1,91 @@
     6.4 +%&latex
     6.5 +%% Derived from: `cvctan.tex'
     6.6 +
     6.7 +\documentclass[a4paper]{article}
     6.8 +
     6.9 +\usepackage{tabularx}
    6.10 +
    6.11 +%\usepackage{doublespace}
    6.12 +%\setstretch{1.1}
    6.13 +
    6.14 +%\usepackage{ae}
    6.15 +\usepackage[T1]{fontenc}
    6.16 +\usepackage{CV}
    6.17 +
    6.18 +
    6.19 +\oddsidemargin 0in
    6.20 +\evensidemargin 0in
    6.21 +\textwidth\paperwidth
    6.22 +\advance \textwidth by -2in
    6.23 +\topmargin 0in
    6.24 +\textheight\paperheight
    6.25 +\advance\textheight -2in
    6.26 +\headheight 0pt
    6.27 +\headsep 0pt
    6.28 +\footskip 0pt
    6.29 +
    6.30 +
    6.31 +%%%%%%%%%%%%%%%%%%%%%%
    6.32 +\begin{document}
    6.33 +
    6.34 +\pagestyle{empty}
    6.35 +\bibliographystyle{plain}
    6.36 +%Ueberschrift
    6.37 +\begin{center}
    6.38 +\huge{\textsc{Publication List}}
    6.39 +\vspace{\baselineskip}
    6.40 +
    6.41 +\Large{\textsc{Sean Halle}}
    6.42 +\end{center}
    6.43 +%\vspace{1.5\baselineskip}
    6.44 +
    6.45 +
    6.46 +\section{Overview} Sean has produced a large body of work, however due to a number of factors has only recently begun concentrating on publishing in major conferences and journals.  As such, most of the publications in the list are technical reports, or papers downloadable from development websites.
    6.47 +
    6.48 +
    6.49 +\cite{BLISHome,
    6.50 +HotPar10_w_BLIS,
    6.51 +HotPar11_w_Stack,
    6.52 +PStackHome,
    6.53 +VMS_LCPC_11,
    6.54 +VMSHome,
    6.55 +WorkTableHome,
    6.56 +BaCTiLTechRep,
    6.57 +CIPTechRep,
    6.58 +CTOSTechRep,
    6.59 +CTPlatformTechRep,
    6.60 +CTRTTechRep,
    6.61 +DKUTechRep_09,
    6.62 +EQNLangTechRep,
    6.63 +GainFromChaos_Halle_92,
    6.64 +MentalFrameworkTechRep_06,
    6.65 +Halle_GainFromChaos_pub,
    6.66 +Halle_Secure_pub,
    6.67 +Halle_SpreadSpect_pub}
    6.68 +
    6.69 +\bibliography{bib_for_papers_apr_2012}
    6.70 +
    6.71 +
    6.72 +
    6.73 +\end{document}
    6.74 +
    6.75 +
    6.76 +
    6.77 +
    6.78 +
    6.79 +%Tabellen
    6.80 +\begin{table}[htbp] \centering%
    6.81 +\begin{tabular}{lll}\hline\hline
    6.82 +1 & 2 & 3 \\ \hline
    6.83 +1 & \multicolumn{2}{c}{2} \\
    6.84 +\hline
    6.85 +\end{tabular}
    6.86 +\caption{Titel\label{Tabelle: Label}}
    6.87 +\end{table}
    6.88 +
    6.89 +
    6.90 +
    6.91 +
    6.92 +
    6.93 +
    6.94 +

     7.1 Binary file CVs/12_Ap__LLNL_CV/LLNL_CV_w_pubs.pdf has changed

     8.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     8.2 +++ b/CVs/12_Ap__LLNL_CV/LLNL_CV_w_pubs.tex	Fri May 04 05:26:00 2012 -0700
     8.3 @@ -0,0 +1,285 @@
     8.4 +%&latex
     8.5 +%% Derived from: `cvctan.tex'
     8.6 +
     8.7 +\documentclass[a4paper]{article}
     8.8 +
     8.9 +\usepackage{tabularx}
    8.10 +
    8.11 +%\usepackage{doublespace}
    8.12 +%\setstretch{1.1}
    8.13 +
    8.14 +%\usepackage{ae}
    8.15 +\usepackage[T1]{fontenc}
    8.16 +\usepackage{CV}
    8.17 +
    8.18 +
    8.19 +\oddsidemargin 0in
    8.20 +\evensidemargin 0in
    8.21 +\textwidth\paperwidth
    8.22 +\advance \textwidth by -2in
    8.23 +\topmargin 0in
    8.24 +\textheight\paperheight
    8.25 +\advance\textheight -2in
    8.26 +\headheight 0pt
    8.27 +\headsep 0pt
    8.28 +\footskip 0pt
    8.29 +
    8.30 +
    8.31 +%%%%%%%%%%%%%%%%%%%%%%
    8.32 +\begin{document}
    8.33 +
    8.34 +\pagestyle{empty}
    8.35 +\bibliographystyle{plain}
    8.36 +%Ueberschrift
    8.37 +\begin{center}
    8.38 +\huge{\textsc{Curriculum Vitae}}
    8.39 +\vspace{\baselineskip}
    8.40 +
    8.41 +\Large{\textsc{Sean Halle}}
    8.42 +\end{center}
    8.43 +%\vspace{1.5\baselineskip}
    8.44 +
    8.45 +\section{}
    8.46 +\noindent\hspace*{\tabcolsep}
    8.47 +\begin{minipage}{0.4\linewidth}
    8.48 +
    8.49 +{\large{\textsc{Address}}}\\
    8.50 +17 Einsteinufer Rm 647 \\
    8.51 +10587 Berlin\\[3pt]
    8.52 +Tel~: +49~30~314~73130\\
    8.53 +EMail~: \texttt{sean.halle@tu-berlin.de}
    8.54 +\end{minipage}
    8.55 +\begin{minipage}{0.4\linewidth}
    8.56 +
    8.57 +{\large{\textsc{Personal Details}}}\\
    8.58 +Nationality: US\\
    8.59 +Gender: Male\\
    8.60 +\\
    8.61 +
    8.62 +\end{minipage}
    8.63 +
    8.64 +\section{Overview/Summary} Sean is a researcher and sometimes entrepreneur.  As an undergraduate and masters student, his research at UC Berkeley demonstrated the first evidence of secure communication using chaos, spread spectrum communication using a chaotic carrier signal, and gain from perturbation of chaotic circuits, with a total of 450+ citations to these papers.  He left with his Masters in 1994, to pursue starting a company with technology developed during a graduate course, eventually founding a fabless chip company around a MIMD-SIMD low-power massively parallel processor for graphics (ProSide), in 1997.  After the company's demise, he switched to software and worked his way up the chain, ending at Chief Software Architect at Nevik in 2000.  The dot-com crash precipitated a return to academia to start his PhD in 2003, where he worked on parallelism, developing a theory of parallel computation, and a performance-portable software stack. As part of this, in 2008 he was invited by Albert Cohen to work in Paris at INRIA, the national computer science research institute for France, concentrating on new parallel languages for high productivity and high performance portability.  This led to BLIS and VMS, two technologies that became the basis of his dissertation, for which he received his PhD in 2011.  He is currently a post-doctorate researcher at TU Berlin, focusing on processor architecture to support portable parallelism, and a software stack to support performance-portable parallel languages, and would like to continue this work in his next post-doctorate position.
    8.65 +
    8.66 +
    8.67 +
    8.68 +\section{Education}
    8.69 +
    8.70 +\begin{CV}
    8.71 +\item[May 1992:] UC Berkeley, BSEE, Dept. of Electrical Engineering and Computer Science.
    8.72 +\item[May 1994:] UC Berkeley, MSEE,  Dept. of Electrical Engineering and Computer Science.
    8.73 +
    8.74 +Thesis on \emph{Experimental Chaos}.  Published the first papers in the field on "Gain from Chaos," "Spread Spectrum Communication Using Chaos," and "Secure Communication Using Chaos." The papers, combined, have garnered in excess of 450 citations. Advisor: Leon O Chua.
    8.75 +
    8.76 +\item[June 2011:] UC Santa Cruz, PhD,  Dept. of Computer Engineering.
    8.77 +
    8.78 +Dissertation on \emph{theory of parallel computation and tools for delivering performance-portable parallel software}. Advisors: Albert Cohen (INRIA, Paris), and Jose Renau (UC Santa Cruz).
    8.79 +
    8.80 +\end{CV}
    8.81 +
    8.82 +
    8.83 +\section{Experience}
    8.84 +
    8.85 +\begin{CV}
    8.86 +
    8.87 +\item[Jun '11 to Jun '12:]  Post-doctorate researcher at Technical University Berlin.
    8.88 +
    8.89 + Overseeing 6 students who are working  on: verifying the Holistic Model of Parallel Computation (proposed in Dissertation), design of a low-power GPU that is free from programming and application restrictions, improvement of Virtualized Master-Slave (VMS) (from Dissertation), and implementation of the HWSim language on top of VMS. 
    8.90 +
    8.91 +\item[Apr '08 to Apr '11:]  INRIA, Paris and Ecole Normale Supereur: Performed research on Portable High Performance Parallelism.  
    8.92 +
    8.93 +In 2008-2009 period demonstrated DKU and BLIS framework in Java and in C, running on multi-core shared memory machines, a heterogeneous collection of them and on the Cell processor.  In 2010 and 2011 designed WorkTable language for high productivity parallel coding for Enterprise applications, and HWSim for high-performance simulation of hardware designs, using parallel host machines. In 2011 delivered Virtualized Master-Slave (VMS), a hardware abstraction to simplify creation and implementation of domain-specific parallel languages, and the basis of a software stack for performant-portable parallel software.  The work there formed the main results in his dissertation.
    8.94 +
    8.95 +\item[Sept '03 to Apr '08:] UC Santa Cruz: Performed research on a theory of parallel computation, and developed a programming system for performance-portable software called CodeTime, in addition to an analytic performance model for out-of-order pipelines.
    8.96 +
    8.97 +\item[Apr '02 to Sept '03:]  Freelance: In anticipation of starting a fabless chip company, architected an ultra low power multi-threaded high-throughput processor.  Developed a detailed analytic model of the processor.  Wrote behavioral code and a test suite to demonstrate its performance.  Pursued series-A funding.  
    8.98 +
    8.99 +\item[Dec '00 to Apr '02:] Nevik Networks: As Chief Software Architect, designed and was responsible for the team implementing a telecom abstraction layer that provides web-based end-customer provisioning of big-iron class 5 switches as well as soft-switches.  Led development, drove requirements gathering and scoping of the product.
   8.100 +
   8.101 +\item[Dec '99 to Dec '00:] SRI International:  A member of SRI's enterprise software consulting spin-off.  Designed a high speed trading system for Deutsche Bank's fixed income securities market.  Co-architected, for American Century, an integrated financial system.  Contributed papers analyzing and detailing electronic exchanges.  Technical lead on implementation of a financial planning services exchange.
   8.102 +
   8.103 +\item[Apr '99 to Dec '99:] Cisco Systems, contract:  Member of web based ordering tool team (\$15 Billion in orders annually via this tool).  Added functionality via modifying front-end servlet code, back-end business logic, and Oracle database tables.
   8.104 +
   8.105 +\item[Apr '98 to Mar '99:] Sun Microsystems, JavaSoft division,  contract:   Participated in debug of the AWT portion of the Java language for the 1.2 release.  Contributed to specification of the automated GUI testing API that later appeared in release 1.5.  Developed automated testing tools.
   8.106 +
   8.107 +\item[Mar '96 to Dec '97:] ProSide Inc.  Acquired funding for a novel architecture fusing SIMD and SPMD of his design.  Targeted at 3D graphics, was also a general "loop accelerator" that appeared as smart-memory.  Developed base programming language and tools.
   8.108 +
   8.109 +\item[Jan '95 to Jan '96:] Digital Equipment Corporation:  Held position created for him by Dan Dobberpuhl to evaluate advanced technologies for use in Alpha processors.  Evaluated adiabatic logic, Time-Stationary Computation, and other low power, high speed technologies.  Invented five new logic families and a novel division technique based on deduction.  Designed high speed pseudo-self-timed array multiplier for low cost Alpha core and StrongArm VLIW co-processor using a combination of static, domino, and differential cascode (DCVSL) logic.
   8.110 +
   8.111 +
   8.112 +\end{CV}
   8.113 +
   8.114 +\pagebreak
   8.115 +\section{Personal References}
   8.116 +
   8.117 +\noindent These persons are familiar with my professional qualifications and my character:
   8.118 +
   8.119 +\begin{table}[ht]
   8.120 +\begin{tabular}{@{}lll@{}}
   8.121 +\textbf{Prof. Albert Cohen} \\
   8.122 +Thesis supervisor & Phone: & +33-1-44-32-21-67\\
   8.123 +Department d'Informatiqe & Email & albert.cohen@inria.fr\\
   8.124 +Ecole Normale Superieure \\
   8.125 +45 rue d'Ulm\\
   8.126 +75005 Paris\\
   8.127 +France
   8.128 +\end{tabular}
   8.129 +
   8.130 +\vspace{.15in}
   8.131 +\begin{tabular}{@{}lll@{}}
   8.132 +\textbf{Prof. Jose Renau} \\
   8.133 +Thesis supervisor & Phone: & +1-831-459-1847\\
   8.134 + 1156 High Street MS: SOE2 & Email & renau@soe.ucsc.edu\\
   8.135 +Santa Cruz, CA 95064 \\
   8.136 +USA
   8.137 +\end{tabular}
   8.138 +
   8.139 +
   8.140 +\vspace{.15in}
   8.141 +\begin{tabular}{@{}lll@{}}
   8.142 +\textbf{Prof. Ben Juurlink} \\
   8.143 +Post-doc Advisor & Phone: & +49 30 314 73131\\
   8.144 +Technical University Berlin & Email &  b.juurlink@tu-berlin.de\\
   8.145 +Einsteinufer 17 / Sekr. EN12 \\
   8.146 +10587 Berlin\\
   8.147 +Germany
   8.148 +\end{tabular}
   8.149 +
   8.150 +\end{table}
   8.151 +
   8.152 +
   8.153 +\section{Refereed Papers}
   8.154 +
   8.155 +\bibitem{Halle_GainFromChaos_pub}
   8.156 +K.S. Halle, Leon~O. Chua, V.S. Anishchenko, and M.A. Safonova.
   8.157 +\newblock Signal amplification via chaos: Experimental evidence.
   8.158 +\newblock {\em Int. J. of Bifurcation and Chaos}, pages 290--308, 1993.
   8.159 +
   8.160 +\bibitem{Halle_SpreadSpect_pub}
   8.161 +K.S. Halle, C.W. Wu, M.~Itoh, and L.~O. Chua.
   8.162 +\newblock Spread spectrum communication through modulation of chaos.
   8.163 +\newblock {\em Int. J. of Bifurcation and Chaos}, pages 469--477, 1993.
   8.164 +\newblock cited by 232.
   8.165 +
   8.166 +\bibitem{Halle_Secure_pub}
   8.167 +V.~Kocarev, K.S. Halle, K.~Eckert, L.~O. Chua, and V.~Parlitz.
   8.168 +\newblock Experimental demonstration of secure communications via chaotic
   8.169 +  synchronization.
   8.170 +\newblock {\em Int. J. of Bifurcation and Chaos}, pages 709--713, 1992.
   8.171 +\newblock cited by 457.
   8.172 +
   8.173 +\bibitem{HotPar10_w_BLIS}
   8.174 +Sean Halle and Albert Cohen.
   8.175 +\newblock Leveraging semantics attached to function calls to isolate
   8.176 +  applications from hardware.
   8.177 +\newblock In {\em HOTPAR '10: USENIX Workshop on Hot Topics in Parallelism},
   8.178 +  June 2010.
   8.179 +
   8.180 +\bibitem{VMS_LCPC_11}
   8.181 +Sean Halle and Albert Cohen.
   8.182 +\newblock A mutable hardware abstraction to replace threads.
   8.183 +\newblock {\em 24th International Workshop on Languages and Compilers for
   8.184 +  Parallel Languages (LCPC11)}, 2011.
   8.185 +
   8.186 +\bibitem{HotPar11_w_Stack}
   8.187 +Sean Halle and Albert Cohen.
   8.188 +\newblock Support of collective effort towards performance portability.
   8.189 +\newblock In {\em HOTPAR '11: USENIX Workshop on Hot Topics in Parallelism},
   8.190 +  May 2011.
   8.191 +
   8.192 +\section{Non-refereed Papers}
   8.193 +
   8.194 +\bibitem{CIPTechRep}
   8.195 +Sean Halle.
   8.196 +\newblock The case for an integrated software platform for {HEC} illustrated
   8.197 +  using the codetime platform, 2005.
   8.198 +\newblock
   8.199 +  http://www.soe.ucsc.edu/share/technical-reports/2005/ucsc-crl-05-05.pdf.
   8.200 +
   8.201 +\bibitem{BaCTiLTechRep}
   8.202 +Sean Halle.
   8.203 +\newblock Bactil: Base codetime language, 2006.
   8.204 +\newblock
   8.205 +  http://www.soe.ucsc.edu/share/technical-reports/2006/\\ucsc-crl-06-08.pdf.
   8.206 +
   8.207 +\bibitem{CTPlatformTechRep}
   8.208 +Sean Halle.
   8.209 +\newblock The elements of the codetime software platform, 2006.
   8.210 +\newblock
   8.211 +  http://www.soe.ucsc.edu/share/\\technical-reports/2006/ucsc-crl-06-09.pdf.
   8.212 +
   8.213 +\bibitem{MentalFrameworkTechRep_06}
   8.214 +Sean Halle.
   8.215 +\newblock A mental framework for use in creating hardware independent parallel
   8.216 +  languages, 2006.
   8.217 +\newblock
   8.218 +  http://www.soe.ucsc.edu/share/technical-reports/2006/ucsc-crl-06-12.pdf.
   8.219 +
   8.220 +\bibitem{CTRTTechRep}
   8.221 +Sean Halle.
   8.222 +\newblock A scalable and efficient peer-to-peer run-time system for a hardware
   8.223 +  independent software platform, 2006.
   8.224 +\newblock
   8.225 +  http://www.soe.ucsc.edu/share/technical-reports/2006/ucsc-crl-06-10.pdf.
   8.226 +
   8.227 +\bibitem{EQNLangTechRep}
   8.228 +Sean Halle.
   8.229 +\newblock An extensible parallel language, 2009.
   8.230 +\newblock
   8.231 +  http://www.soe.ucsc.edu/share/technical-reports/2009/\\ucsc-soe-09-16.pdf.
   8.232 +
   8.233 +\bibitem{CTOSTechRep}
   8.234 +Sean Halle.
   8.235 +\newblock A hardware-independent parallel operating system abstraction layer
   8.236 +  for parallelism, 2009.
   8.237 +\newblock
   8.238 +  http://www.soe.ucsc.edu/share/technical-reports/2009/ucsc-soe-09-15.pdf.
   8.239 +
   8.240 +\bibitem{PStackHome}
   8.241 +Sean Halle.
   8.242 +\newblock {PStack} home page -- a software stack for performantly portable
   8.243 +  parallelism, 2012.
   8.244 +\newblock http://pstack.\\sourceforge.net.
   8.245 +
   8.246 +\bibitem{WorkTableHome}
   8.247 +Sean Halle.
   8.248 +\newblock The worktable language reference manual, 2012.
   8.249 +\newblock http://musictwodotoh.com/worktable/content/\\refman.pdf.
   8.250 +
   8.251 +\bibitem{BLISHome}
   8.252 +Sean Halle and Albert Cohen.
   8.253 +\newblock {BLIS} website, November 2008.
   8.254 +\newblock http://blisplatform.sourceforge.net.
   8.255 +
   8.256 +\bibitem{DKUTechRep_09}
   8.257 +Sean Halle and Albert Cohen.
   8.258 +\newblock DKU pattern for performance portable parallel software, 2009.
   8.259 +\newblock
   8.260 +  http://www.soe.\\ucsc.edu/share/technical-reports/2009/ucsc-soe-09-06.pdf.
   8.261 +
   8.262 +\bibitem{VMSHome}
   8.263 +Sean Halle, Merten Sach, Ben Juurlink, and Albert Cohen.
   8.264 +\newblock {VMS} home page, 2010.
   8.265 +\newblock http://virtualizedmasterslave.\\org.
   8.266 +
   8.267 +\end{document}
   8.268 +
   8.269 +
   8.270 +
   8.271 +
   8.272 +
   8.273 +%Tabellen
   8.274 +\begin{table}[htbp] \centering%
   8.275 +\begin{tabular}{lll}\hline\hline
   8.276 +1 & 2 & 3 \\ \hline
   8.277 +1 & \multicolumn{2}{c}{2} \\
   8.278 +\hline
   8.279 +\end{tabular}
   8.280 +\caption{Titel\label{Tabelle: Label}}
   8.281 +\end{table}
   8.282 +
   8.283 +
   8.284 +
   8.285 +
   8.286 +
   8.287 +
   8.288 +

     9.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     9.2 +++ b/CVs/12_Ap__LLNL_CV/bib_for_papers_apr_28_2012.bib	Fri May 04 05:26:00 2012 -0700
     9.3 @@ -0,0 +1,916 @@
     9.4 +@techrep{SyncConstr_impl_w_distr_coherence_HW_Utah_96,
     9.5 +	author = {Carter, J. B. and Kuo, C.-C. and Kuramkote, R.},
     9.6 +	title = { A comparison of software and hardware synchronization mechanisms for distributed shared memory multiprocessors},
     9.7 +	institution = {University of Utah, Salt Lake City, UT},
     9.8 +	year = 1996,
     9.9 +	url = {http://www.cs.utah.edu/research/techreports/1996/pdf/UUCS-96-011.pdf},
    9.10 +	number = {UUCS-96-011}
    9.11 +}
    9.12 +@Article{SWCoherence_Hill_SW_for_shared_coherence_w_HW_support_93,
    9.13 +	author = {Hill, Mark D. and Larus, James R. and Reinhardt, Steven K. and Wood, David A.},
    9.14 +	title = {Cooperative shared memory: software and hardware for scalable multiprocessors},
    9.15 +	journal = {ACM Trans. Comput. Syst.},
    9.16 +	volume = 11,
    9.17 +	number = 4,
    9.18 +	year = 1993,
    9.19 +	pages = {300--318}
    9.20 +}
    9.21 +@InProceedings{SWCache_MIT_embedSW_manages_cache_w_HW_supp,
    9.22 +	author = {Chiou, Derek and Jain, Prabhat and Rudolph, Larry and Devadas, Srinivas},
    9.23 +	title = {Application-specific memory management for embedded systems using software-controlled caches},
    9.24 +	booktitle = {DAC},
    9.25 +	year = 2000,
    9.26 +	pages = {416--419}
    9.27 +}
    9.28 +@InProceedings{SWCache_instr_trig_HW_supp_04,
    9.29 +	author = {Janapsatya, Andhi and Parameswaran, Sri and Ignjatovic, A.},
    9.30 +	title = {Hardware/software managed scratchpad memory for embedded system},
    9.31 +	booktitle = {Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design},
    9.32 +	series = {ICCAD '04},
    9.33 +	year = 2004,
    9.34 +	pages = {370--377}
    9.35 +}
    9.36 +@InProceedings{SWCache_arch_supp_OS_policy_06,
    9.37 +	author = {Rafique, Nauman and Lim, Won-Taek and Thottethodi, Mithuna},
    9.38 +	title = {Architectural support for operating system-driven CMP cache management},
    9.39 +	booktitle = {Proceedings of the 15th international conference on Parallel architectures and compilation techniques},
    9.40 +	series = {PACT '06},
    9.41 +	year = 2006,
    9.42 +	pages = {2--12}
    9.43 +}
    9.44 +@InProceedings{SWCoherence_on_Distr_Mem_90,
    9.45 +	author = {Bennett, J.K. and Carter, J.B. and Zwaenepoel, W.},
    9.46 +	booktitle = {Computer Architecture, 1990. Proceedings., 17th Annual International Symposium on},
    9.47 +	title = {Adaptive software cache management for distributed shared memory architectures},
    9.48 +	year = 1990,
    9.49 +	pages = {125 -134}
    9.50 +}
    9.51 +@InProceedings{Charm_runtime_opt_10,
    9.52 +	author = {Mei, Chao and Zheng, Gengbin and Gioachin, Filippo and Kal{\'e}, Laxmikant V.},
    9.53 +	title = {Optimizing a parallel runtime system for multicore clusters: a case study},
    9.54 +	booktitle = {The 2010 TeraGrid Conference},
    9.55 +	year = 2010,
    9.56 +	pages = {12:1--12:8}
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   9.220 +	year = 2006
   9.221 +}
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   9.226 +	year = 2009
   9.227 +}
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   9.239 +}
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   9.245 +}
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